Patents by Inventor Chun-Mai Liu
Chun-Mai Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8626580Abstract: A semiconductor coupon-service system, includes a coupon-service module for managing a semiconductor service; a coupon generator, in connection with the semiconductor service, for generating a coupon associated with the semiconductor service; and a coupon maintainer, in connection with the semiconductor service, for processing coupon operations associated with the coupon.Type: GrantFiled: August 31, 2006Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chi Chin, Shouh-Dauh Fred Lin, Lawrence Chen, Chun-Mai Liu, Huang-Sheng Lin
-
Publication number: 20070156526Abstract: A semiconductor coupon-service system, includes a coupon-service module for managing a semiconductor service; a coupon generator, in connection with the semiconductor service, for generating a coupon associated with the semiconductor service; and a coupon maintainer, in connection with the semiconductor service, for processing coupon operations associated with the coupon.Type: ApplicationFiled: August 31, 2006Publication date: July 5, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Chi CHIN, Shouh-Dauh Fred LIN, Lawrence CHEN, Chun-Mai LIU, Huang-Sheng LIN
-
Patent number: 7038297Abstract: Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range ?40 C to +85 C. Furthermore, the temperature variation at room temperature (˜25 C) can be reduced to nearly zero.Type: GrantFiled: January 21, 2004Date of Patent: May 2, 2006Assignee: Winbond Electronics CorporationInventors: Paul Vande Voorde, Chun-Mai Liu
-
Patent number: 6922046Abstract: An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.Type: GrantFiled: April 2, 2004Date of Patent: July 26, 2005Assignee: Winbond Electronics CorporationInventors: Chun-Mai Liu, Hagop A. Nazarian
-
Publication number: 20040241952Abstract: Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range −40 C to +85 C. Furthermore, the temperature variation at room temperature (˜25 C) can be reduced to nearly zero.Type: ApplicationFiled: January 21, 2004Publication date: December 2, 2004Inventors: Paul Vande Voorde, Chun-Mai Liu
-
Publication number: 20040196020Abstract: An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.Type: ApplicationFiled: April 2, 2004Publication date: October 7, 2004Inventors: Chun-Mai Liu, Hagop A. Nazarian
-
Patent number: 6744244Abstract: An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.Type: GrantFiled: April 1, 2002Date of Patent: June 1, 2004Assignee: Winbond Electronics CorporationInventors: Chun-Mai Liu, Hagop A. Nazarian
-
Patent number: 6716700Abstract: A method of forming a semiconductor memory having rows and columns of memory cells is as follows; forming a plurality of rows of program gate lines from a second layer polysilicon; forming a plurality of rows of select gate lines from a third polysilicon layer; forming a plurality of rows of diffusion source lines: forming a plurality of local bitlines from a first layer metal, the cells along each column being divided into a pre-designated number of groups, and drains of the cells in each group being connected to a local bitline extending across the cells in the group of cells; and forming a plurality of global bitlines from a second layer metal extending along every two columns of cells, each global bitline being configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.Type: GrantFiled: April 21, 2003Date of Patent: April 6, 2004Assignee: Windbond Electronics CorporationInventors: Chun-Mai Liu, Albert Kordesch, Ming-Bing Chang
-
Patent number: 6709943Abstract: Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range −40 C to +85 C. Furthermore, the temperature variation at room temperature (˜25 C) can be reduced to nearly zero.Type: GrantFiled: August 26, 2002Date of Patent: March 23, 2004Assignee: Winbond Electronics CorporationInventors: Paul Vande Voorde, Chun-Mai Liu
-
Publication number: 20040036144Abstract: Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range −40C to +85C. Furthermore, the temperature variation at room temperature (˜25C) can be reduced to nearly zero.Type: ApplicationFiled: August 26, 2002Publication date: February 26, 2004Inventors: Paul Vande Voorde, Chun-Mai Liu
-
Publication number: 20030201467Abstract: A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.Type: ApplicationFiled: April 21, 2003Publication date: October 30, 2003Applicant: Winbond Electronics CorporationInventors: Chun-Mai Liu, Albert Kordesch, Ming-Bing Chang
-
Patent number: 6631060Abstract: A field oxide device (FOD) useful for electrostatic discharge (ESD) protection and other applications. The FOD is characterized as being capable of achieving a relatively low breakdown voltage and capable of handling relatively high currents during an ESD event. In general, the FOD includes a zener junction to promote an earlier breakdown of the device. The zener junction also provides a planar-like breakdown region which makes it capable of handling relatively high currents. In particular, the FOD includes a p-doped substrate having a drain-side n+ diffusion region and a source-side n+ diffusion region which are separated by a field oxide. The FOD further includes a p+ doped region that interfaces with the drain-side n+ diffusion region to form a zener junction. The breakdown voltage of the FOD can be easily set by controlling the doping concentration and energy of the p+ doped region.Type: GrantFiled: November 30, 2000Date of Patent: October 7, 2003Assignee: Winbond Electronics CorporationInventors: Kung-Yen Su, Chun-Mai Liu, Kaiman Chan
-
Publication number: 20030184312Abstract: An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.Type: ApplicationFiled: April 1, 2002Publication date: October 2, 2003Inventors: Chun-Mai Liu, Hagop A. Nazarian
-
Patent number: 6563733Abstract: A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.Type: GrantFiled: May 24, 2001Date of Patent: May 13, 2003Assignee: Winbond Electronics CorporationInventors: Chun-Mai Liu, Albert Kordesch, Ming-Bing Chang
-
Publication number: 20030052361Abstract: A method for fabricating a triple self-aligned non-volatile memory device is disclosed. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.Type: ApplicationFiled: October 29, 2002Publication date: March 20, 2003Inventors: Chun-Mai Liu, Kung-Yen Su, Kai-Man Chan, Albert V. Kordesch
-
Publication number: 20030034510Abstract: A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.Type: ApplicationFiled: May 24, 2001Publication date: February 20, 2003Inventors: Chun-Mai Liu, Albert Kordesch, Ming-Bing Chang
-
Patent number: 6492231Abstract: A method for fabricating a triple self-aligned non-volatile memory device is disclosed. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.Type: GrantFiled: June 8, 2001Date of Patent: December 10, 2002Assignee: Winbond Electronics CorporationInventors: Chun-Mai Liu, Kung-Yen Su, Kai-Man Chan, Albert V. Kordesch
-
Patent number: 6493199Abstract: A silicon controlled rectifier (SCR) serving as an electrostatic discharge (ESD) protection device having a vertical zener junction for triggering breakdown. The SCR includes a p-doped substrate having an n-doped well, spaced-apart p+ and n+ doped regions for cathode connection formed within the n-doped well, and spaced-apart p+ and n+ doped regions for anode connection formed with the p-substrate external to the n-doped well. The SCR further includes a vertical zener junction situated between the anode n+ doped region and the n-well. The vertical zener junction has a p+ doped region sandwiched between two n+ doped regions. The n+ doped region of the vertical zener junction closest to the n-well may extend at least partially within the n-well, or be totally outside of the n-well.Type: GrantFiled: October 26, 2000Date of Patent: December 10, 2002Assignee: Winbond Electronics CorporationInventors: Kung-Yen Su, Chun-Mai Liu, Wei-Fan Chen
-
Patent number: 6489200Abstract: A method of forming a capacitor on a substrate includes forming a first polysilicon layer overlying the substrate to define a floating gate. A second polysilicon overlying the first polysilicon layer is formed to define a control gate and a first electrode of the capacitor. A dielectric layer is formed over the second polysilicon layer. A third polysilicon layer is formed over the dielectric layer. The third polysilicon layer is etched to define a second electrode of the capacitor. Thereafter the dielectric layer is etched.Type: GrantFiled: July 11, 2000Date of Patent: December 3, 2002Assignee: Winbond Electronics CorporationInventors: Len-Yi Leu, Chun-Mai Liu, Ken Su, Albert V. Kordesch
-
Publication number: 20020063289Abstract: A field oxide device (FOD) useful for electrostatic discharge (ESD) protection and other applications. The FOD is characterized as being capable of achieving a relatively low breakdown voltage and capable of handling relatively high currents during an ESD event. In general, the FOD includes a zener junction to promote an earlier breakdown of the device. The zener junction also provides a planar-like breakdown region which makes it capable of handling relatively high currents. In particular, the FOD includes a p-doped substrate having a drain-side n+ diffusion region and a source-side n+ diffusion region which are separated by a field oxide. The FOD further includes a p+ doped region that interfaces with the drain-side n+ diffusion region to form a zener junction. The breakdown voltage of the FOD can be easily set by controlling the doping concentration and energy of the p+ doped region.Type: ApplicationFiled: November 30, 2000Publication date: May 30, 2002Inventors: Kung-Yen Su, Chun-Mai Liu, Kaiman Chan