Patents by Inventor Chun-Min Cheng
Chun-Min Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9337209Abstract: A method of fabricating a semiconductor device, including the following steps. A plurality of fin structures are formed on a substrate. There is a trench between the fin structures. At least two times of circulating processes are performed. The circulating processes include: a deposition process and an etching process. The deposition process is performed to fill a first conductor material layer in the trench. The first conductor material layer covers top parts and sidewalls of the fin structures. The etching process is performed to remove a part of the first conductor material layer.Type: GrantFiled: December 31, 2014Date of Patent: May 10, 2016Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Ling Chiang, Chun-Min Cheng
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Publication number: 20160086966Abstract: A method of manufacturing a semiconductor device is provided. Gate structures are formed on a substrate, and a first dielectric layer having grooves is formed between two adjacent gate structures. An upper surface of the first dielectric layer is lower than an upper surface of the gate structures. Afterwards, an intermediate layer is formed to cover the gate structures, the first dielectric layer, and the grooves, and openings are formed therein. Each opening is formed between two adjacent gate structures, and the first dielectric layer is removed through the opening. Next, a second dielectric layer is foamed on the intermediate layer, so as to define an air gap between two adjacent gate structures. Furthermore, a semiconductor device is provided.Type: ApplicationFiled: September 24, 2014Publication date: March 24, 2016Inventors: Pei-Ci Jhang, Chun-Min Cheng
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Patent number: 9287287Abstract: Present example embodiments relate generally to methods of fabricating a semiconductor device, and semiconductor devices thereof, comprising providing a substrate, forming an insulating base layer on the substrate, and disposing a conductive layer on the insulating base layer at an initial temperature. The methods further comprise increasing the initial temperature at a first increase rate to a first increased temperature and performing an in-situ annealing process to the conductive layer at the first increased temperature. The methods further comprise increasing the first increased temperature at a second increase rate to a second increased temperature, and forming an insulating layer after performing the in-situ annealing process at the second increased temperature.Type: GrantFiled: December 18, 2013Date of Patent: March 15, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Jung-Yi Guo, Chun-Min Cheng
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Patent number: 9224749Abstract: Present example embodiments relate generally to semiconductor devices and methods of fabricating a semiconductor device comprising forming an insulating base layer over a surface of a substrate. The method further comprises forming a multilayer over the insulating base layer, the multilayer having conducting and insulating layers. The method further comprises etching a pattern in the multilayer and forming a charge storage layer over the patterned multilayer. The method further comprises forming a protective silicon layer over the charge storage layer, followed by performing a heat treatment process.Type: GrantFiled: June 4, 2014Date of Patent: December 29, 2015Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Jung-Yi Guo, Chun-Min Cheng
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Publication number: 20150357340Abstract: Present example embodiments relate generally to semiconductor devices and methods of fabricating a semiconductor device comprising forming an insulating base layer over a surface of a substrate. The method further comprises forming a multilayer over the insulating base layer, the multilayer having conducting and insulating layers. The method further comprises etching a pattern in the multilayer and forming a charge storage layer over the patterned multilayer. The method further comprises forming a protective silicon layer over the charge storage layer, followed by performing a heat treatment process.Type: ApplicationFiled: June 4, 2014Publication date: December 10, 2015Inventors: Jung-Yi Guo, Chun-Min Cheng
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Publication number: 20150171105Abstract: Present example embodiments relate generally to methods of fabricating a semiconductor device, and semiconductor devices thereof, comprising providing a substrate, forming an insulating base layer on the substrate, and disposing a conductive layer on the insulating base layer at an initial temperature. The methods further comprise increasing the initial temperature at a first increase rate to a first increased temperature and performing an in-situ annealing process to the conductive layer at the first increased temperature. The methods further comprise increasing the first increased temperature at a second increase rate to a second increased temperature, and forming an insulating layer after performing the in-situ annealing process at the second increased temperature.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Jung-Yi GUO, Chun-Min CHENG
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Patent number: 8872260Abstract: An apparatus of and method for making a semiconductor structure having a shallow trench isolation (STI) trench with a substantially v-shaped profile, that is the distance between top portions is greater than the distance between bottom portions of shallow trench isolation (STI) structure sidewalls adjacent to the trench, provides for substantially seamless and substantially void-free gate structures. The semiconductor structures are formed by implanting an implantation species into the sidewalls, which allows for the top portions of the sidewalls to be etched away at a greater rate than that of the bottom portions, resulting in the substantially v-shaped profile. And the substantially v-shaped profile allows for subsequent device layers to more easily and smoothly fill in the v-shaped trenches, due to a wider opening toward the tops of the trenches.Type: GrantFiled: June 5, 2012Date of Patent: October 28, 2014Assignee: Macronix International Co., Ltd.Inventors: Jung-Yi Guo, Chun-Min Cheng
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Publication number: 20130320484Abstract: An apparatus of and method for making a semiconductor structure having a shallow trench isolation (STI) trench with a substantially v-shaped profile, that is the distance between top portions is greater than the distance between bottom portions of shallow trench isolation (STI) structure sidewalls adjacent to the trench, provides for substantially seamless and substantially void-free gate structures. The semiconductor structures are formed by implanting an implantation species into the sidewalls, which allows for the top portions of the sidewalls to be etched away at a greater rate than that of the bottom portions, resulting in the substantially v-shaped profile. And the substantially v-shaped profile allows for subsequent device layers to more easily and smoothly fill in the v-shaped trenches, due to a wider opening toward the tops of the trenches.Type: ApplicationFiled: June 5, 2012Publication date: December 5, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: JUNG-YI GUO, CHUN-MIN CHENG
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Patent number: 8581327Abstract: A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.Type: GrantFiled: December 21, 2010Date of Patent: November 12, 2013Assignee: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, Yen-Hao Shih, Ling-Wu Yang, Chun-Min Cheng
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Patent number: 8298952Abstract: An isolation structure comprising a substrate is provided. A trench is in the substrate. A sidewall of the trench has a first inclined surface and a second inclined surface. The first inclined surface is located on the second inclined surface. The slope of the first inclined surface is different from the slope of the second inclined surface. A length of the first inclined surface is greater than 15 nanometers.Type: GrantFiled: January 17, 2012Date of Patent: October 30, 2012Assignee: Macronix International Co., Ltd.Inventors: Ming-Tsung Wu, Shih-Ping Hong, Chun-Min Cheng, Yu-Chung Chen, Han-Hui Hsu
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Publication number: 20120115304Abstract: An isolation structure comprising a substrate is provided. A trench is in the substrate. A sidewall of the trench has a first inclined surface and a second inclined surface. The first inclined surface is located on the second inclined surface. The slope of the first inclined surface is different from the slope of the second inclined surface. A length of the first inclined surface is greater than 15 nanometers.Type: ApplicationFiled: January 17, 2012Publication date: May 10, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ming-Tsung Wu, Shih-Ping Hong, Chun-Min Cheng, Yu-Chung Chen, Han-Hui Hsu
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Patent number: 8120140Abstract: An isolation structure comprising a substrate is provided. A trench is in the substrate. A sidewall of the trench has a first inclined surface and a second inclined surface. The first inclined surface is located on the second inclined surface. The slope of the first inclined surface is different from the slope of the second inclined surface. A length of the first inclined surface is greater than 15 nanometers.Type: GrantFiled: May 22, 2009Date of Patent: February 21, 2012Assignee: Macronix International Co., Ltd.Inventors: Ming-Tsung Wu, Shih-Ping Hong, Chun-Min Cheng, Yu-Chung Chen, Han-Hui Hsu
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Publication number: 20110089480Abstract: A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.Type: ApplicationFiled: December 21, 2010Publication date: April 21, 2011Applicant: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, Yen-Hao Shih, Ling-Wu Yang, Chun-Min Cheng
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Patent number: 7879706Abstract: A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.Type: GrantFiled: October 31, 2007Date of Patent: February 1, 2011Assignee: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, Yen-Hao Shih, Ling-Wu Yang, Chun-Min Cheng
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Publication number: 20100295147Abstract: An isolation structure comprising a substrate is provided. A trench is in the substrate. A sidewall of the trench has a first inclined surface and a second inclined surface. The first inclined surface is located on the second inclined surface. The slope of the first inclined surface is different from the slope of the second inclined surface. A length of the first inclined surface is greater than 15 nanometers.Type: ApplicationFiled: May 22, 2009Publication date: November 25, 2010Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ming-Tsung Wu, Shih-Ping Hong, Chun-Min Cheng, Yu-Chung Chen, Han-Hui Hsu
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Publication number: 20090108331Abstract: A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Applicant: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, Yen-Hao Shih, Ling-Wu Yang, Chun-Min Cheng