Patents by Inventor Chun-Min Lin

Chun-Min Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978678
    Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: May 7, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Tung-Kai Liu, Tsau-Hua Hsieh, Wei-Cheng Chu, Chun-Hsien Lin, Chandra Lius, Ting-Kai Hung, Kuan-Feng Lee, Ming-Chang Lin, Tzu-Min Yan, Hui-Chieh Wang
  • Publication number: 20240145460
    Abstract: An integrated circuit includes a T-coil circuit, a silicon-controlled rectifier (SCR), and a signal-loss prevention circuit. The T-coil circuit is coupled to an input/output (I/O) pad and an internal circuit. The SCR is coupled to the T-coil circuit and the internal circuit. The signal-loss prevention circuit is coupled to the T-coil circuit and the SCR. The signal-loss prevention circuit includes a resistor coupled to the T-coil circuit and the SCR. An electrostatic current flows through the resistor and turns on the SCR. The signal-loss prevention circuit may also include a diode circuit coupled to the T-coil circuit and the SCR. The diode circuit is configured to prevent signal loss.
    Type: Application
    Filed: January 3, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Min WU, Ming-Dou KER, Chun-Yu LIN, Li-Wei CHU
  • Publication number: 20240139199
    Abstract: The present disclosure provides a use of a pharmaceutical composition including adenine and/or a pharmaceutically acceptable salt thereof in a manufacture of a medicament for treating diabetic ulcers, and the medicament can effectively accelerate and enhance wound healing of diabetic ulcers and prevent scar formation.
    Type: Application
    Filed: March 25, 2022
    Publication date: May 2, 2024
    Inventors: Jen-Yi Chio, Han-Min Chen, Jiun-Tsai Lin, Yi-Fang Cheng, Guang-Huar Young, Chun-Fang Huang
  • Publication number: 20240134470
    Abstract: An electronic device includes a first insulating layer, a first conductive portion, a second conductive portion, a transistor, and an electronic unit. The first insulating layer has a first opening penetrating the first insulating layer along a first direction. The first conductive portion is disposed in the first opening. The second conductive portion is electrically connected to the first conductive portion. The transistor is electrically connected to the second conductive portion. The electronic unit is electrically connected to the first conductive portion. In a cross-sectional view of the electronic device, the electronic unit and the second conductive portion are disposed on two opposite sides of the first insulating layer respectively, the first conductive portion has a first length along a second direction perpendicular to the first direction, the second conductive portion has a second length along the second direction, and the first length is different from the second length.
    Type: Application
    Filed: January 4, 2024
    Publication date: April 25, 2024
    Applicant: InnoLux Corporation
    Inventors: Po-Yang Chen, Hsing-Yuan Hsu, Tzu-Min Yan, Chun-Hsien Lin, Kuei-Sheng Chang
  • Patent number: 11942543
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
  • Publication number: 20240072158
    Abstract: A method of forming a FinFET is disclosed. The method includes depositing a conductive material across each of a number of adjacent fins, depositing a sacrificial mask over the conductive material, patterning the conductive material with the sacrificial mask to form a plurality of conductive material segments, depositing a sacrificial layer over the sacrificial mask, and patterning the sacrificial layer, where a portion of the patterned sacrificial layer remains over the sacrificial mask, where a portion of the sacrificial mask is exposed, and where the exposed portion of the sacrificial mask extends across each of the adjacent fins. The method also includes removing the portion of the sacrificial layer over the sacrificial mask, after removing the portion of the sacrificial layer over the sacrificial mask, removing the sacrificial mask, epitaxially growing a plurality of source/drain regions from the semiconductor substrate, and electrically connecting the source/drain regions to other devices.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Sung-Hsin Yang, Jung-Chi Jeng, Ru-Shang Hsiao, Kuo-Min Lin, Z.X. Fan, Chun-Jung Huang, Wen-Yu Kuo
  • Patent number: 11914804
    Abstract: A touch display device is provided in this disclosure. The touch display device includes a substrate, a first conductive layer, a second conductive layer, a stacked structure, an inorganic light emitting unit, and a touch sensing circuit. The first conductive layer is disposed on the substrate. The first conductive layer includes a gate electrode. The second conductive layer is disposed on the first conductive layer. The second conductive layer includes a source electrode and a drain electrode. The stacked structure is disposed on the substrate. The stacked structure includes a conductive channel and a sensing electrode. The inorganic light emitting unit is disposed on the stacked structure. The inorganic light emitting unit is electrically connected with the drain electrode via the conductive channel. The touch sensing circuit is electrically connected with the sensing electrode.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: February 27, 2024
    Assignee: InnoLux Corporation
    Inventors: Po-Yang Chen, Hsing-Yuan Hsu, Tzu-Min Yan, Chun-Hsien Lin, Kuei-Sheng Chang
  • Publication number: 20230068435
    Abstract: Semiconductor die assemblies with sidewall protection, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes an interface die with a low-k dielectric layer and a stack of semiconductor dies attached to the interface die. The semiconductor die assembly also includes a molding structure that protects sidewalls of the interface die and sidewalls of the semiconductor dies. In some embodiments, the semiconductor die assembly includes a passivation layer attached to the interface die opposite to the stack of semiconductor dies. Further, the passivation layer may include a sidewall surface coplanar with an outer sidewall surface of the molding structure. The passivation layer may include a ledge underneath the molding structure, which is uncovered by the interface die. The semiconductor die assembly may include a NCF material at the sidewalls of the stack of semiconductor dies, where the molding structure surrounds the NCF material.
    Type: Application
    Filed: February 9, 2022
    Publication date: March 2, 2023
    Inventors: Yu Lin Kao, Chun Min Lin, Sui Chi Huang, Pei Sian Shao
  • Patent number: 11152295
    Abstract: A semiconductor package structure includes a first package including a bonding region and a periphery region surrounding the bonding region, at least one insulating structure disposed in the bonding region of the first package, a second package disposed over the first package and the insulating structure in the bonding region, and a plurality of connectors disposed between the first package and the second package. The plurality of connectors provide electrical connection between the first package and the second package. Further, the insulating structure penetrates the first package and is spaced apart from the plurality of connectors.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Hao Lin, Chien-Kuo Chang, Tzu-Kai Lan, Hui-Ting Lin, Chun-Min Lin
  • Publication number: 20200135991
    Abstract: A lighting device is disclosed, including an LED die, a light-transmissive encapsulant and a light-transmissive wall. The light-transmissive encapsulant covers the light-emitting side surfaces and the top surface, and the light-transmissive wall surrounds the light-transmissive encapsulant and covers the side surfaces of the light-transmissive encapsulant. Furthermore, the refractive index of the light-transmissive encapsulant is not greater than the refractive index of the light-transmissive wall. A lighting module is further disclosed, including a circuit substrate and the lighting devices, as described above, which are disposed on the circuit substrate. Therefore, when lights generated from the LED die are transmitted into the light-transmissive wall from the light-transmissive encapsulant, the lights will be deflected towards the lateral direction, thereby increasing the viewing angle of the lighting device.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 30, 2020
    Applicant: Everlight Electronics Co., Ltd.
    Inventors: Chun-Min LIN, Bo Cheng JIANG, Shang-Fu KAO, Yu Ju CHEN, Jen-hsiung LAI, Chung Chuan HSIEH
  • Publication number: 20190318987
    Abstract: A semiconductor package structure includes a first package including a bonding region and a periphery region surrounding the bonding region, at least one insulating structure disposed in the bonding region of the first package, a second package disposed over the first package and the insulating structure in the bonding region, and a plurality of connectors disposed between the first package and the second package. The plurality of connectors provide electrical connection between the first package and the second package. Further, the insulating structure penetrates the first package and is spaced apart from the plurality of connectors.
    Type: Application
    Filed: April 13, 2018
    Publication date: October 17, 2019
    Inventors: CHIH-HAO LIN, CHIEN-KUO CHANG, TZU-KAI LAN, HUI-TING LIN, CHUN-MIN LIN
  • Publication number: 20190051800
    Abstract: A light emitting diode (LED) device and a method of manufacturing the LED device aforementioned are provided. The LED device (400) includes a LED chip (430), an encapsulant (440) and a ring-shape barrier (450?). The LED chip has a first surface and a reflection surface, and the encapsulant covers the LED chip. Wherein the reflection surface (450a) is inclined with respect to a side surface (430b) of the LED chip. A light output angle can be effectively adjusted, and the needs to re-design lenses when market demand changes may be reduced.
    Type: Application
    Filed: November 9, 2016
    Publication date: February 14, 2019
    Applicant: EVERLIGHT ELECTRONICS CO., LTD.
    Inventors: Chih-Min LIN, Tsung-Lin LU, Wei-Tyng YU, Robert YEH, Chung-Chuan HSIEH, Chun-Min LIN
  • Publication number: 20170025395
    Abstract: A light emitting device including a first work circuit and a second work circuit is provided. The first work circuit includes a first LED chip and a first bonding adhesive. The first LED chip and the first bonding adhesive are electrically connected in series. The second work circuit includes a second LED chip. When an operation current of the first work circuit and an operation current of the second work circuit are the same, the first work circuit has a first voltage VW1 and the second work circuit has a second voltage VW2, wherein VW1?VW2.
    Type: Application
    Filed: July 22, 2016
    Publication date: January 26, 2017
    Inventors: Chien-Chih Chen, Ya Chin Tu, Chun Min Lin, Chieh-Yu Kang
  • Publication number: 20160300963
    Abstract: A solar cell with high-reflectivity region and narrow etch mark is disclosed. The solar cell includes a semiconductor substrate having a first surface and a second surface, a low-reflectivity region in and on the semiconductor substrate, and an annular etch mark disposed on the first surface and surrounding the low-reflectivity region. The etch mark is located along the perimeter of the first surface and has an average width that is not greater than 2 mm. The second surface is a surface with high reflectivity.
    Type: Application
    Filed: January 4, 2016
    Publication date: October 13, 2016
    Inventors: Chia-Pang Kuo, Shr-Han Feng, Chun-Min Lin