Abstract: A method of forming a complementary field-effect transistor (CFET) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurali

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: An optoelectronic semiconductor device includes a substrate, a first type semiconductor structure located on the substrate, a second type semiconductor structure located on the first type semiconductor structure, an active structure located between the first type semiconductor structure and the second type semiconductor structure, a plurality of contact portions disposed between the first type semiconductor structure and the substrate, and a first conductive oxide layer, a second conductive oxide layer, a first insulating layer and a second insulating layer. The plurality of contact portions is separated from each other, and one of them includes a semiconductor and has a side wall. The first conductive oxide layer contacts the contact portion, and the second conductive oxide layer contacts the first conductive oxide layer. The first insulating layer contacts the side wall. The second insulating layer is disposed between the first insulating layer and the second conductive oxide layer.

Abstract: A semiconductor device includes a semiconductor stack, a reflective structure, and a conductive structure. The semiconductor stack includes a first semiconductor structure, a second semiconductor structure and an active region located between the first semiconductor structure and the second semiconductor structure. The reflective structure is located at a side of semiconductor stack closed to the first semiconductor structure, and includes a first metal. The conductive structure locates between the reflective structure and the first semiconductor structure, and includes a first region overlapping with the active structure and a second region which does not overlap with the active structure. The first metal in the second region has a concentration smaller than 5 atomic percent.

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

Abstract: A semiconductor device is provided, which includes a semiconductor stack and a first contact structure. The semiconductor stack includes an active layer and has a first surface and a second surface. The first contact structure is located on the first surface and includes a first semiconductor layer, a first metal element-containing structure and a first p-type or n-type layer. The first metal element-containing structure includes a first metal element. The first p-type or n-type layer physically contacts the first semiconductor layer and the first metal element-containing structure. The first p-type or n-type layer includes an oxygen element (O) and a second metal element and has a thickness less than or equal to 20 nm, and the first semiconductor layer includes a phosphide compound or an arsenide compound.

Abstract: A two-phase immersion-type heat dissipation structure having fins for facilitating bubble generation is provided. The two-phase immersion-type heat dissipation structure includes a heat dissipation substrate, and a plurality of fins. The heat dissipation substrate has a fin surface and a non-fin surface that face away from each other, the non-fin surface is configured to be in contact with a heat source immersed in a two-phase coolant, and the fin surface is connected with the plurality of fins. More than half of the fins are functional fins, and at least one side surface of each of the functional fins and the fin surface have an included angle therebetween that is from 80 degrees to 100 degrees. A center line average roughness (Ra) of the side surface is less than 3 ?m, and a ten-point average roughness (Rz) of the side surface is not less than 12 ?m.

Abstract: An optoelectronic semiconductor device includes a substrate, a first type semiconductor structure, a second type semiconductor structure, an active structure and a contact structure. The first type semiconductor structure is located on the substrate and has a first protrusion part with a first thickness and a platform part with a second thickness. The second type semiconductor structure is located on the first type semiconductor structure. The active structure is between the first type semiconductor structure and the second type semiconductor structure. The contact structure is disposed between the first type semiconductor structure and the substrate. The second thickness of the platform part is in a range of 0.01 ?m to 1 ?m.

Abstract: A two-phase immersion-cooling heat-dissipation structure having skived fins with high surface roughness includes an immersion-cooling substrate and a plurality of skived fins. The immersion-cooling substrate has a top surface and a bottom surface that are opposite to each other, the bottom surface is used for contacting a heat source immersed in a two-phase coolant, the top surface is connected with the plurality of skived fins, a center line average roughness Ra of a surface of the plurality of skived fins is greater than 10 ?m, and a ten point average roughness Rz of the surface of the plurality of skived fins is greater than 20 ?m, such that a ratio between a surface area of the plurality of skived fins in contact with the two-phase coolant and a volume of the plurality of skived fins is greater than 400.

Abstract: A two-phase immersion-cooling heat-dissipation structure having shortened evacuation route for vapor bubbles includes an immersion-cooling substrate having a first surface and a second surface that are opposite to each other and immersion-cooling fins. The second surface contacts a heat source immersed in a two-phase coolant, and the first surface connects to the immersion-cooling fins. The immersion-cooling fins include at least one skived fin integrally formed on the first surface of the immersion-cooling substrate by skiving, and further include at least one functional fin. The functional fin is a single continuous fin extends lengthwise in a vapor bubbles evacuation direction, has a central portion corresponding in position to the heat source and upper and lower end portions located away from the heat source, and a height of the central portion is greater than at least one of a height of the upper and lower end portions.

Abstract: A two-phase immersion-cooling heat-dissipation structure having skived fins includes an immersion-cooling substrate and a plurality of immersion-cooling fins. The immersion-cooling substrate has a top surface and a bottom surface that are opposite to each other, the bottom surface is used for contacting a heat-generating component immersed in a two-phase coolant, the top surface is connected with the plurality of immersion-cooling fins, the plurality of immersion-cooling fins include at least one skived fin integrally formed on the top surface of the immersion-cooling substrate, and the plurality of immersion-cooling fins are non-linearly arranged. A thickness of any one of the plurality of immersion-cooling fins ranges from 0.1 mm to 0.35 mm, a height of any one of the plurality of immersion-cooling fins ranges from 5 mm to 10 mm, and a gap between any two of the plurality of immersion-cooling fins ranges from 0.1 mm to 0.35 mm.

Abstract: A power module package structure includes a first substrate and a power component. The first substrate includes at least one conductive layer on a surface thereof. The power component includes a first chip and a first spacer. The first chip has at least one electrode. The first spacer in a heat dissipation space between the first substrate and the first chip includes an insulating heat dissipation layer in the heat dissipation space and multiple vertical conductive connectors, each of the vertical conductive connectors penetrates the insulating heat dissipation layer. The insulating heat dissipation layer surrounds the vertical conductive connectors and electrically isolates the vertical conductive connectors. The vertical conductive connector includes two opposite ends, one end electrically connected to the conductive layer, and the other end electrically connected to the electrode to form a conductive path and a heat dissipation path between the first chip and the first substrate.

Abstract: A two-phase immersion-type heat dissipation device is provided. The two-phase immersion-type heat dissipation device includes a heat dissipation substrate and a plurality of reinforced fins. The heat dissipation substrate has a first surface and a second surface configured to be in contact with a heating element. The first surface is opposite to the second surface and is arranged away from the heating element. The plurality of reinforced fins are integrally formed on the first surface of the heat dissipation substrate, and a thickness of each of the plurality of reinforced fins is less than 1 mm. According to a scanning electron microscopy image of electron backscattered diffraction, a median of local misorientation distribution of the plurality of reinforced fins is greater than 1.6 times a median of local misorientation distribution of the heat dissipation substrate.

Abstract: A two-phase immersion-type composite heat dissipation device is provided, which includes a heat dissipation substrate, a plurality of fins, and a surface porous layer. The heat dissipation substrate has a first surface and a second surface. The first surface is configured to be in contact with a heat source, and the second surface is opposite to the first surface and is distant from the heat source. A projection region of the heat dissipation substrate that corresponds to the heat source is defined as a high-temperature region, and a low-temperature region is defined at an outer periphery of the high-temperature region. The fins are opposite to the heat source, and are disposed within the high-temperature region of the second surface of the heat dissipation substrate. The surface porous layer is disposed within a range of the low-temperature region of the heat dissipation substrate.

Abstract: The present disclosure provides a toughened resin composition, which includes: (A) a toughened and modified compound, which includes a styrene maleic anhydride compound, an anhydride grafted olefin polymer, and a diisocyanate compound; (B) a thermosetting polymer; and (C) a toughening resin; wherein, in the toughened and modified compound, the diisocyanate compound forms a polyimide bond with the styrene maleic anhydride compound and the anhydride grafted olefin polymer, respectively. The present disclosure has high toughness and excellent mechanical properties; thus, it may have a wide range of applications in the fields of electronics, aerospace and the like.

Abstract: A package structure includes a first substrate, a second substrate, a plurality of dies, a plurality of first conductive elements, and a plurality of second conductive elements. The first substrate has a recessed region. The second substrate is disposed in the recessed region and protrudes from the first substrate. The dies are disposed on the first substrate and the second substrate, such that the second substrate is disposed between the first substrate and the dies. The first conductive elements are disposed between the dies and the first substrate. The dies are electrically connected with the first substrate through the first conductive elements. The second conductive elements are disposed between the dies and the second substrate. The dies are electrically connected with the second substrate through the second conductive elements.

Abstract: A package structure includes a first substrate, a second substrate, a plurality of dies, a plurality of first conductive elements, and a plurality of second conductive elements. The first substrate has a recessed region. The second substrate is disposed in the recessed region and protrudes from the first substrate. The dies are disposed on the first substrate and the second substrate, such that the second substrate is disposed between the first substrate and the dies. The first conductive elements are disposed between the dies and the first substrate. The dies are electrically connected with the first substrate through the first conductive elements. The second conductive elements are disposed between the dies and the second substrate. The dies are electrically connected with the second substrate through the second conductive elements.

Abstract: A package structure includes a first substrate, a second substrate, a plurality of dies, a plurality of first conductive elements, and a plurality of second conductive elements. The first substrate has a recessed region. The second substrate is disposed in the recessed region and protrudes from the first substrate. The dies are disposed on the first substrate and the second substrate, such that the second substrate is disposed between the first substrate and the dies. The first conductive elements are disposed between the dies and the first substrate. The dies are electrically connected with the first substrate through the first conductive elements. The second conductive elements are disposed between the dies and the second substrate. The dies are electrically connected with the second substrate through the second conductive elements.