Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.

Abstract: A light-adjusting device having first regions and second regions is provided. The light-adjusting device includes pillars that form several groups of meta structures. The groups of meta structures correspond to the first regions, and from a top view, the first regions and the second regions are arranged in a checkerboard pattern.

Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.

Abstract: A blood pressure device includes a first blood pressure measuring device, a second blood pressure measuring device, and a controller. The first blood pressure measuring device is to be worn on a first position of a wrist so as to obtain a first blood pressure information of the first position. The second blood pressure measuring device is to be worn on a second position of the wrist so as to obtain a second blood pressure information of the second position. The controller is electrically coupled to the first blood pressure measuring device and the second blood pressure measuring device so as to adjust tightness between the expanders and the user's skin, respectively. The controller receives, processes, and calculates a pulse transit time between the first blood pressure information and the second blood pressure information, and the controller obtains at least one blood pressure value based on the pulse transit time.

Abstract: A centrifugal heat dissipation fan including a housing and an impeller disposed in the housing on an axis is provided. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions. A heat dissipation system of an electronic device is also provided.

Abstract: A method of providing over-the-air assistance information for interference cancellation or suppression to the receiver is proposed. Under a first solution, a two-stage DCI (downlink control information) or SCI (sidelink control information) scheduling method is proposed. The set of first-stage DCI or SCI provides a part of scheduling information which is beneficial for interference cancellation or suppression and is broadcasted by a transmitter or scheduler to all receivers. The set of second-stage DCI or SCI includes the remaining scheduling information and is unicasted by a transmitter or scheduler to each receiver. Under a second solution, assistance information DCI for interference cancellation or suppression is broadcasted by a transmitter or scheduler to all receivers.

Abstract: A method of providing over-the-air assistance information for interference cancellation or suppression to the receiver is proposed. Under a first solution, a two-stage DCI (downlink control information) or SCI (sidelink control information) scheduling method is proposed. The set of first-stage DCI or SCI provides a part of scheduling information which is beneficial for interference cancellation or suppression and is broadcasted by a transmitter or scheduler to all receivers. The set of second-stage DCI or SCI includes the remaining scheduling information and is unicasted by a transmitter or scheduler to each receiver. Under a second solution, assistance information DCI for interference cancellation or suppression is broadcasted by a transmitter or scheduler to all receivers.

Abstract: A method of providing over-the-air assistance information for interference cancellation or suppression to the receiver is proposed. Under a first solution, a two-stage DCI (downlink control information) or SCI (sidelink control information) scheduling method is proposed. The set of first-stage DCI or SCI provides a part of scheduling information which is beneficial for interference cancellation or suppression and is broadcasted by a transmitter or scheduler to all receivers. The set of second-stage DCI or SCI includes the remaining scheduling information and is unicasted by a transmitter or scheduler to each receiver. Under a second solution, assistance information DCI for interference cancellation or suppression is broadcasted by a transmitter or scheduler to all receivers.

Abstract: A frequency-generating circuit includes a frequency synthesizer circuit and a controller. The frequency synthesizer circuit generates a radio-frequency clock signal according to a reference clock signal and a channel number. The controller is coupled to the frequency synthesizer circuit, generates a power-down control signal for controlling at least a portion of the frequency synthesizer circuit to power down. The frequency synthesizer circuit includes an accumulator for generating an accumulated value according to the channel number. The frequency synthesizer circuit generates the radio-frequency clock signal according to the reference clock signal and the accumulated value. The controller maintains the accumulated value of the accumulator when the portion of the frequency synthesizer circuit powers down.

Abstract: A frequency-generating circuit includes a frequency synthesizer circuit and a reference clock signal processor. The frequency synthesizer circuit receives a processed reference clock signal and generates a radio-frequency clock signal according to the processed reference clock signal. The reference clock signal processor receives an original reference clock signal from an oscillator and processes the original reference clock signal according to an indication signal to generate the processed reference clock signal. The indication signal is generated according to a required reference clock frequency of a communications apparatus. When the required reference clock frequency is high, a frequency of the processed reference clock signal is a multiple of a frequency of the original reference clock signal, and when the required reference clock frequency is low, the frequency of the original reference clock signal is a multiple of the frequency of the processed reference clock signal.

Abstract: A communications apparatus includes a radio transceiver and a processor. The radio transceiver transmits or receives wireless radio frequency signals to communicate with a first network device. The processor estimates a first Doppler frequency shift value corresponding to a first carrier frequency utilized for communicating with the first network device, and adjusts the first carrier frequency to an adjusted first carrier frequency according to the first Doppler frequency shift value and communicates with the first network device according to the adjusted first carrier frequency via the radio transceiver or adjusts a first value of a measured signal quality of the first network device to an adjusted first value according to the first Doppler frequency shift value and transmits a first measurement report with the adjusted first value via the radio transceiver to the first network device.

Abstract: An embodiment of the invention provides a method to be performed by a first wireless communication apparatus in communicating with a second wireless communication apparatus. First, the first wireless communication apparatus determines whether a plurality of sub-channels are simultaneously available for the second wireless communication apparatus. Then, the first wireless communication apparatus simultaneously uses the sub-channels to transmit a plurality of divergent copies of a data segment to the second wireless communication apparatus, respectively, if the sub-channels are simultaneously available for the second wireless communication apparatus.

Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.

Abstract: A frequency synthesizer includes a digitally controlled oscillator, a sigma-delta modulation circuit and a controller. The digitally controlled oscillator is arranged to generate an oscillating clock. The sigma-delta modulation circuit is arranged to generate an SDM input to the digitally controlled oscillator. The controller is arranged to adjust an operating frequency of the SDM circuit in response to a transmit power level of a transmitter using the oscillating clock.

Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.

Abstract: A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one resistance-capacitance (RC) detection result, wherein the digital compensation filter includes an RC compensation module; and tuning the digital compensation filter by inputting the RC detection result into the RC compensation module. For example, the RC detection result may correspond to a detected value representing a product of a resistance value and a capacitance value. In another example, the at least one RC detection result may be obtained by performing RC detection on at least a portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein. An associated digital compensation filter and an associated calibration circuit are also provided.

Abstract: A clock generator utilized for providing a clock signal includes: a first oscillator and a switching circuit. The switching circuit is coupled to the first oscillator and a second oscillator, and utilized for receiving a first oscillating signal generated from the first oscillator and a second oscillating signal generated from the second oscillator, and selecting one of the first oscillating signal and the second oscillating signal as the clock signal according to a status signal.

Abstract: An embodiment of the invention provides a method of processing a radio frequency (RF) signal. According to the embodiment, the RF signal is first synthesized with a synthesis signal to generate a synthesized signal. Then, the synthesized signal is filtered with a filtering bandwidth to generate a filtered signal. Next, the filtered signal is converted into digital data. Then, the digital data is processed to analyze a plurality of carriers within the filtering bandwidth as presented in the RF signal.

Abstract: A clock generator for a mobile device, capable of operating in one of a full-power mode and a low-power mode according to a standby signal to generate a high-frequency clock signal and a low-frequency clock signal is disclosed. The clock generator includes a crystal oscillator, for generating an oscillation signal of a specific frequency according to the power mode of the clock generator; a frequency division block, for dividing the oscillation signal by a specific divisor according to the power mode of the clock generator to generate the low-frequency clock signal; and a buffer block, for amplifying the oscillation signal to generate the high-frequency clock signal; wherein during each power mode, a frequency of the low-frequency clock signal is substantially the same.

Abstract: A method and apparatus for performing real time clock (RTC) calibration through frame number calculation are provided, where the method is applied to an electronic device. The method includes the steps of: before power failure of the electronic device occurs, obtaining an original time value from an RTC of the electronic device and storing the original time value and a frame number of a first frame into a storage unit; and after the electronic device is powered on since elimination of the power failure, obtaining a frame number of a second frame and performing at least one calculation operation according to the frame number of the second frame, the frame number of the first frame, and the original time value to determine a calibrated time value of the RTC, and updating the RTC with at least one of the calibrated time value and a derivative of the calibrated time value.