Abstract: DRAM cell structures and methods for manufacturing the same are provided. The DRAM cell structure includes a semiconductor substrate having a well region and an original semiconductor surface, an access transistor located within the well region and having a gate structure, a bit line electrically coupled to the access transistor, a storage capacitor electrically coupled to the access transistor, a word line electrically coupled to the gate structure of the access transistor, an isolation structure within the well region and surrounding the access transistor, and a conductive interconnection structure positioned within the isolation structure and electrically connected to the well region of the semiconductor substrate.

Abstract: A transistor structure includes a gate conductive region, a gate dielectric region, a channel region and a drain region. The gate conductive region is below an original surface of a substrate. The gate dielectric region surrounds the gate conductive region. The channel region surrounds the gate dielectric region. The drain region is horizontally spaced apart from the gate conductive region, wherein the drain region includes a highly doped region; wherein the gate dielectric region includes a first dielectric portion and a second dielectric portion, the first dielectric portion is positioned between the gate conductive region and the highly doped region, and the second dielectric portion is positioned between the gate conductive region and the channel region; wherein a horizontal thickness of the first dielectric portion is greater than that of the second dielectric portion.

Abstract: A memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a signal electrode and a counter electrode, the capacitor is over the transistor, and the signal electrode is electrically coupled to the second conductive region of the transistor and isolated from the first conductive region of the transistor. The counter electrode includes a plurality of sub-electrodes electrically connected with each other.

Abstract: A memory structure includes a semiconductor substrate, an active region, a transistor, and a buried-WL (word line). The semiconductor substrate has an original semiconductor surface. The active region is in the semiconductor substrate and surrounded by a shallow trench isolation (STI) region. The transistor is formed based on the active region. The buried-WL (word line) extends through the active region and the STI region. The buried-WL has variable depth or width along the extension direction of the buried-WL.

Abstract: A transistor structure includes a semiconductor substrate, a gate region a spacer, a first trench, a first isolation region and a conductive region. The semiconductor substrate has an active region which has a semiconductor surface. The gate region has a first conductive portion over the semiconductor surface of the semiconductor substrate in the active region and a second conductive portion over the first conductive portion. The spacer covers a sidewall of the gate region. The first trench is formed below the semiconductor surface of the semiconductor substrate in the active region. The first isolation region is in the first trench. The conductive region is positioned on the first isolating region. Wherein a lateral length of the first conductive portion is greater than that of the second conductive portion.

Abstract: The present invention provides an audio recording method and an associated audio processing circuit. The recording method includes performing an initialization of an audio processing circuit at a first timing, setting a gain of the audio processing circuit to a first value at a second timing, using the audio processing circuit to start recording at a third timing, completing the initialization of the audio processing circuit at a fourth timing, and adjusting the gain of the audio processing circuit to a second value at a fifth timing. The second value is greater than the first value, the first timing and the second timing are earlier than the third timing, the fourth timing is later than the third timing, and the fifth timing is later than the third timing.

Abstract: A transistor structure includes a gate conductive region, a gate dielectric region, a channel region and a drain region. The gate conductive region is below an original surface of a substrate. The gate dielectric region surrounds the gate conductive region. The channel region surrounds the gate dielectric region. The drain region is horizontally spaced apart from the gate conductive region, wherein the drain region includes a highly doped region; wherein the gate dielectric region includes a first dielectric portion and a second dielectric portion, the first dielectric portion is positioned between the gate conductive region and the highly doped region, and the second dielectric portion is positioned between the gate conductive region and the channel region; wherein a horizontal thickness of the first dielectric portion is greater than that of the second dielectric portion.

Abstract: A control method for a storage device of a driving recorder includes: configuring a directory entry of a storage device according to a predetermined directory entry stored in a storage unit; configuring a file allocation table of the storage device according to a predetermined file allocation table stored in the storage unit; and controlling a controller to write data to the storage device according to the directory entry and the file allocation table. In one embodiment, entries of the predetermined file allocation table are interleaved to accommodate multiple files and still support a continuous write operation.

Abstract: A control method for a storage device of a driving recorder includes: configuring a directory entry of a storage device according to a predetermined directory entry stored in a storage unit; configuring a file allocation table of the storage device according to a predetermined file allocation table stored in the storage unit; and controlling a controller to write data to the storage device according to the directory entry and the file allocation table. In one embodiment, entries of the predetermined file allocation table are interleaved to accommodate multiple files and still support a continuous write operation.