Abstract: The single-step debug card using the PCI interface according to the present invention utilizes a bus master to send out an REQ# signal to request issuing a control during the PCI bus cycle to be inspected. The address, data, command, and byte enable (BE#) of the bus cycle are locked and displayed through LEDs for single-step debugging. Through a switch circuit, a TRDY# ready signal is sent out. A device selection signal (DEVSEL#) is raised to HIGH at the same time the TRDY# ready signal finishes so as to notify the bus master on the single-step interruption debug card to end the cycle for single-step debugging.

Abstract: A method for verifying clock signal frequency of a sound interface of a computer system is disclosed. The processes include steps of initializing and setting a DMA controller and the sound interface, starting DMA data transfer, resetting a time out counter. During the DMA data transfer, a step of incrementing the time out counter is performed until the selected DMA channel of the DMA controller reaches a terminal count condition. After each increment, it is checked if DMA data transfer is time out. When the DMA channel of the DMA controller reaches the terminal count condition, the current count of the time out counter is compared with a maximum tolerable count and a minimum tolerable count. If the count of the time out counter is between the maximum and minimum tolerable counts, a message indicating the clock signal frequency of the sound interface is correct is issued, otherwise a message indicating the clock signal frequency is incorrect is issued.

Abstract: This specification discloses a single step debug card using the PCI bus, which keeps the FRAME# of the PCI bus at a low voltage; latches and displays through an LED the address and command of the PCI bus cycle; keeps the control signal of read only memory and the IRDY# ready signal and TRDY# ready signal on the PCI bus at a low voltage, latches and displays through an LED the data and byte enable of the PCI bus cycle; outputs a device selection signal from a target device when the target device is detected; intercepts the PCI bus cycle when the device selection signal is kept at a low voltage and both the IRDY# ready signal and the TRDY# ready signal are kept at a low voltage; enables the PCI host to provide a retry function when the target device cannot respond a TRDY# ready signal before the PCI bus cycle ends so as to achieve the function of single step interruption debugging.

Abstract: A method for verifying clock signal frequency of a sound interface of a computer system is disclosed. The processes include steps of initializing and setting a DMA controller and the sound interface, starting DMA data transfer, resetting a time out counter. During the DMA data transfer, a step of incrementing the time out counter is performed until the selected DMA channel of the DMA controller reaches a terminal count condition. After each increment, it is checked if DMA data transfer is time out. When the DMA channel of the DMA controller reaches the terminal count condition, the current count of the time out counter is compared with a maximum tolerable count and a minimum tolerable count. If the count of the time out counter is between the maximum and minimum tolerable counts, a message indicating the clock signal frequency of the sound interface is correct is issued, otherwise a message indicating the clock signal frequency is incorrect is issued.

Abstract: The single-step debug card using the PCI interface according to the present invention utilizes a bus master to send out an REQ# signal to request issuing a control during the PCI bus cycle to be inspected. The address, data, command, and byte enable (BE#) of the bus cycle are locked and displayed through LEDs for single-step debugging. Through a switch circuit, a TRDY# ready signal is sent out. A device selection signal (DEVSEL#) is raised to HIGH at the same time the TRDY# ready signal finishes so as to notify the bus master on the single-step interruption debug card to end the cycle for single-step debugging.

Abstract: This specification discloses a single step debug card using the PCI bus, which keeps the FRAME# of the PCI bus at a low voltage; latches and displays through an LED the address and command of the PCI bus cycle; keeps the control signal of read only memory and the IRDY# ready signal and TRDY# ready signal on the PCI bus at a low voltage, latches and displays through an LED the data and byte enable of the PCI bus cycle; outputs a device selection signal from a target device when the target device is detected; intercepts the PCI bus cycle when the device selection signal is kept at a low voltage and both the IRDY# ready signal and the TRDY# ready signal are kept at a low voltage; enables the PCI host to provide a retry function when the target device cannot respond a TRDY# ready signal before the PCI bus cycle ends so as to achieve the function of single step interruption debugging.