Abstract: A method to process a packet is described herein. The method comprises receiving a packet including a header and a payload. The header is parsed using a packet processor to determine type and priority of the packet. The header is then processed using a hardware acceleration block based on one or more of incoming bandwidth, priority and type of the packet. The custom hardware acceleration block generates header modification data that is sent to the packet processor. The header is modified using the packet processor, based on the header modification data, to generate a modified header. The modified header is appended to the payload and transmitted.

Abstract: A method to transmit data using a device having a plurality of physical input/output (I/O) interfaces is provided. The method comprises receiving data and determining a topology according to which data is to be transmitted. Data is transmitted in sequential order via a single physical interface for a first topology and in random order via a plurality of physical interfaces for a second topology. A System On Chip (SOC) unit enabled to transmit data via one or more physical interfaces is provided. The SOC comprises a processor and a network interface including multiple physical input/output (I/O) interfaces coupled to the processor. In response to receiving data for transmission, the processor is enabled to select a single I/O interface for sequential data transmission according to a first topology or select multiple physical I/O interfaces for random order data transmission according to a second topology.

Abstract: An Parallel and Long Adaptive Instruction Set Architecture (PALADIN) is provided to optimize packet processing. The Instruction Set Architecture (ISA) includes instructions such as aggregate comparison, comparison OR, comparison AND and bitwise instructions. The ISA also includes dedicated packet processing instructions such as hash, predicate, select, checksum and time to live adjust, move header left, post, move header left/right and load/store header/status.

Abstract: A method to process a packet is described herein. The method comprises receiving a packet including a header and a payload. The header is parsed using a packet processor to determine type and priority of the packet. The header is then processed using a hardware acceleration block based on one or more of incoming bandwidth, priority and type of the packet. The custom hardware acceleration block generates header modification data that is sent to the packet processor. The header is modified using the packet processor, based on the header modification data, to generate a modified header. The modified header is appended to the payload and transmitted.

Abstract: A method to transmit data using a device having a plurality of physical input/output (I/O) interfaces is provided. The method comprises receiving data and determining a topology according to which data is to be transmitted. Data is transmitted in sequential order via a single physical interface for a first topology and in random order via a plurality of physical interfaces for a second topology. A System On Chip (SOC) unit enabled to transmit data via one or more physical interfaces is provided. The SOC comprises a processor and a network interface including multiple physical input/output (I/O) interfaces coupled to the processor. In response to receiving data for transmission, the processor is enabled to select a single I/O interface for sequential data transmission according to a first topology or select multiple physical I/O interfaces for random order data transmission according to a second topology.

Abstract: A method and apparatus for programming instruction issuing rules for instructions residing among various virtual channels, as well as the same virtual channel of an I/O bus interface for a system-on-a-chip processor. In the method and apparatus of the present invention both intra-virtual channel dependencies and inter-virtual channel dependencies are fully programmable, thereby offering significant advantages over prior art I/O interfaces. The method and apparatus of the present invention is broadly comprised of a system for managing data transactions between a first bus and a second bus. A first transaction conversion module is operably connected to the first bus and is operable to receive transactions from the first bus and a first format and to convert those transactions into an internal format.