Abstract: The present disclosure provides a memory device including a first electrode; a second electrode; a transistor, and a nanotube. The transistor includes a first node, a second node and a control node, wherein the second node is electrically coupled to the second electrode, and the control node is configured to generate a channel between the first node and the second node. A first end of the nanotube is electrically coupled to a contact, and a second end of the nanotube is positioned between the first electrode and the second electrode. The second end electrically connects the first electrode to form a non-volatile open state of the memory device, or the second end electrically connects the second electrode to form a non-volatile closed state of the memory device. The non-volatile open state represents a first logic state and the non-volatile closed state represents a second logic state.