Abstract: The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.

Abstract: The present application discloses a semiconductor structure and methods for manufacturing semiconductor structures. The semiconductor structure includes a plurality of bottom dies and a top die stacked on the bottom dies. The bottom dies receive power supplies through tiny through silicon vias (TSVs) formed in backside substrates of the bottom dies, while the top die receives power supplies through dielectric vias (TDVs) formed in a dielectric layer that covers the bottom dies. By enabling backside power delivery to the bottom die, more space can be provided for trace routing between stacked dies. Therefore, greater computation capability can be achieved within a smaller chip area with less power loss.

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes first semiconductor die, a second semiconductor die and a memory package. The first semiconductor die and the second semiconductor die are stacked on each other. The first semiconductor die includes a first interface and a third interface. The first interface overlaps and is electrically connected to the second interface arranged on the second semiconductor die. The third interface is arranged on a first edge of the first semiconductor die. The memory package is disposed beside the first semiconductor die, wherein the memory package is electrically connected to the first semiconductor die by the third interface.

Abstract: An electrostatic sensing system configured to sense an electrostatic information of a fluid inside a fluid distribution component and including an electrostatic sensing assembly, a signal amplifier and an analog-to-digital converter. The electrostatic sensing assembly includes a sensing component, and a shield. The sensing component is configured to be disposed at the fluid distribution component. The sensing component is disposed through the fluid distribution component so as to be partially located in the fluid distribution component. The shield surrounds a part of the sensing component that is located in the fluid distribution component. At least part of the shield is located on an upstream side of the sensing component. The signal amplifier is electrically connected to the sensing component. The analog-to-digital converter is electrically connected to the signal amplifier. The shield has an opening spaced apart from the sensing component.

Abstract: A piping system is provided, connecting a plurality of scrubbers which are disposed on a supporting structure, including a collecting pipe and a drain pipe. The collecting pipe has a main body and a plurality of protrusions, wherein the main body has an outer surface and a first central axis. The protrusions are protruding from the outer surface, and the first central axis is perpendicular to the supporting structure. The collecting pipe communicates with the scrubbers via the protrusions. The drain pipe is disposed under the supporting structure and has a second central axis, wherein the collecting pipe is extended through the supporting structure and connects to the drain pipe, and the first central axis is perpendicular to the second central axis.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.

Abstract: A piping system is provided, connecting a plurality of scrubbers which are disposed on a supporting structure, including a collecting pipe and a drain pipe. The collecting pipe has a main body and a plurality of protrusions, wherein the main body has an outer surface and a first central axis. The protrusions are protruding from the outer surface, and the first central axis is perpendicular to the supporting structure. The collecting pipe communicates with the scrubbers via the protrusions. The drain pipe is disposed under the supporting structure and has a second central axis, wherein the collecting pipe is extended through the supporting structure and connects to the drain pipe, and the first central axis is perpendicular to the second central axis.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.

Abstract: An electronic structure includes a substrate body, an electronic package structure and a conductive unit. The electronic package structure is disposed on the substrate body. The electronic package structure includes a first inner electrode portion, a second inner electrode portion, a first outer electrode portion electrically connected to the first inner electrode portion, and a second outer electrode portion electrically connected to the second inner electrode portion. The conductive unit includes a first conductive body and a second conductive body respectively electrically contacting the first and the second outer electrode portions. The electronic package structure has a first notch and a second notch, the first outer electrode portion is extended into the first notch to contact the top surface of the first inner electrode portion, and the second outer electrode portion is extended into the second notch to contact the top surface of the second inner electrode portion.

Abstract: An electronic structure includes a substrate body, an electronic package structure and a conductive unit. The electronic package structure is disposed on the substrate body. The electronic package structure includes a first inner electrode portion, a second inner electrode portion, a first outer electrode portion electrically connected to the first inner electrode portion, and a second outer electrode portion electrically connected to the second inner electrode portion. The conductive unit includes a first conductive body and a second conductive body respectively electrically contacting the first and the second outer electrode portions. The electronic package structure has a first notch and a second notch, the first outer electrode portion is extended into the first notch to contact the top surface of the first inner electrode portion, and the second outer electrode portion is extended into the second notch to contact the top surface of the second inner electrode portion.

Abstract: A ceramic glaze-coating structure of a chip element and a method of forming the same are provided. In the ceramic glaze-coating structure, a high-density, smooth, and high-impedance ceramic glaze is coated on the body of an element. As for the terminal electrode part, the unique firing characteristics between the material of the terminal electrode (e.g., conductive compositions) and the ceramic glaze are utilized, such that the ceramic glaze layer between the surface of the terminal electrode or the terminal electrode and the ceramic body is absorbed and then removed by sintering; thus, the ceramic glaze coating structure of a chip element with only the element body being coated is formed.

Abstract: An exemplary coating apparatus (40) for fabricating a color filter (3) includes a supporting table (44) and a dispenser (48). The supporting table supports a substrate (30) that serves as a foundation of the color filter. The dispenser includes plural first nozzles (412) for spraying a first color photo-resist onto the substrate, plural second nozzles (422) for spraying a second color photo-resist onto the substrate, and plural third nozzles (432) for spraying a third color photo-resist onto the substrate. The first, second and third nozzles simultaneously spray the first, second and third color photo-resists onto respective different locations on the substrate. Therefore three corresponding color resins can be formed on the substrate in a single coating step. Thus, a cost of fabricating the color filter is reduced.

Abstract: A ceramic glaze-coating structure of a chip element and a method of forming the same are provided. In the ceramic glaze-coating structure, a high-density, smooth, and high-impedance ceramic glaze is coated on the body of an element. As for the terminal electrode part, the unique firing characteristics between the material of the terminal electrode (e.g., conductive compositions) and the ceramic glaze are utilized, such that the ceramic glaze layer between the surface of the terminal electrode or the terminal electrode and the ceramic body is absorbed and then removed by sintering; thus, the ceramic glaze coating structure of a chip element with only the element body being coated is formed.

Abstract: A cover-actuated keyboard encoding system is disclosed which can be used either alone or as a part of a universal remote control unit. It contains (a) a keyboard; (b) a memory for storing a plurality of control codes; (c) a special keyboard cover for covering the first keyboard; and (d) a computer program to convert the covered keys of the first keyboard into a control code. The keyboard cover is designed such that it contains one or more key-seat protrusions which are arranged such that they will be pressing against one or more of the first keys when the keyboard cover is closed. A CPU is programmed to scan the key board and convert the scanned keyboard value to a control code, in accordance with the number and locations of the keys that are being pressed during a power-on or a reset.