Patents by Inventor Chun Ping Wang

Chun Ping Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804231
    Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
  • Publication number: 20200312662
    Abstract: A hard mask formed over a patterned photoresist layer in a tri-layer photoresist and a method for patterning a target layer using the same are disclosed. In an embodiment, a method includes depositing a photoresist layer over a first hard mask layer; patterning the photoresist layer to form a plurality of openings in the photoresist layer; depositing a second hard mask layer over the photoresist layer, the second hard mask layer filling the plurality of openings, the second hard mask layer having a first etch selectivity relative to the first hard mask layer, the photoresist layer having a second etch selectivity relative to the first hard mask layer, the first etch selectivity being greater than the second etch selectivity; planarizing the second hard mask layer; removing the photoresist layer; and etching the first hard mask layer using the second hard mask layer as a mask.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Ching-Yu Chang, Jung-Hau Shiu, Szu-Ping Tung, Chun-Kai Chen, Jen Hung Wang, Tze-Liang Lee
  • Patent number: 10770313
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The first redistribution structure has a dielectric layer and a feed line disposed on the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The insulation encapsulation has a protrusion laterally wraps around the feed line. The insulation encapsulation has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The second redistribution structure is disposed on the die and the insulation encapsulation.
    Type: Grant
    Filed: April 21, 2019
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Chung-Hao Tsai, Chun-Lin Lu, Yen-Ping Wang, Che-Wei Hsu
  • Patent number: 10763766
    Abstract: The present teaching relates to a magnetic sensor residing in a housing. The magnetic sensor includes an input port and an output port, both extending from the housing, wherein the input port is to be connected to an external alternating current (AC) power supply. The magnetic sensor also includes an electric circuit which comprises an output control circuit coupled with the output port and configured to be at least responsive to a magnetic induction signal and the external AC power supply to control the magnetic sensor to operate in a state in which a load current flows through the output port. The magnetic induction signal is indicative of at least one characteristic of an external magnetic field detected by the electrical circuit and the operating frequency of the magnetic sensor is positively proportional to the frequency of the external AC power supply.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: September 1, 2020
    Assignee: JOHNSON ELECTRIC INTERNATIONAL AG
    Inventors: Chi Ping Sun, Fei Xin, Ken Wong, Shing Hin Yeung, Hui Min Guo, Shu Zuo Lou, Xiao Ming Chen, Guang Jie Cai, Chun Fai Wong, Shu Juan Huang, Yun Long Jiang, Yue Li, Bao Ting Liu, En Hui Wang, Xiu Wen Yang, Li Sheng Liu, Yan Yun Cui
  • Patent number: 10727082
    Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electric Magnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shou Zen Chang, Chun-Lin Lu, Kai-Chiang Wu, Ching-Feng Yang, Vincent Chen, Chuei-Tang Wang, Yen-Ping Wang, Hsien-Wei Chen, Wei-Ting Lin
  • Publication number: 20200176259
    Abstract: A method includes etching a gate structure to form a trench extending into the gate structure, wherein sidewalls of the trench comprise a metal oxide material, applying a sidewall treatment process to the sidewalls of the trench, wherein the metal oxide material has been removed as a result of applying the sidewall treatment process and filling the trench with a first dielectric material to form a dielectric region, wherein the dielectric region is in contact with the sidewall of the gate structure.
    Type: Application
    Filed: November 12, 2019
    Publication date: June 4, 2020
    Inventors: Chun-Yi Lee, Ting-Gang Chen, Chieh-Ping Wang, Hong-Hsien Ke, Chia-Hui Lin, Tai-Chun Huang
  • Patent number: 10633118
    Abstract: A mobile rustproofing washing system includes a receptacle, a control module, a water supply module, a filtration module and a washing module. The receptacle is removably disposed on a mobile carrier. The control module is disposed in the receptacle. The water supply module is disposed in the receptacle and includes a front water tank and a rear water tank. The filtration module is connected to the front water tank and the rear water tank. The filtration module receives and filters water from the front water tank. The filtered water is stored in the rear water tank. The washing module connects with the rear water tank and receives water therefrom, so as to carry out a washing process. Therefore, the mobile rustproofing washing system is quick to mount/demount and easy to use, thereby having high mobility.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 28, 2020
    Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Yu-Ping Wang, Chin-Cheng Wu, Ming-Jia Wang, Chun-Yu Chen, Yi-Rong Zeng, Kuan-You Liu, Ming-Ta Hsieh, Ching-Wen Fan
  • Patent number: 10634923
    Abstract: A head-mounted display includes a body, a bearing base, a knob, a guiding element, and a head belt set. The knob is pivoted to the bearing base and located outside the bearing base. The guiding element is pivoted to the bearing base and located inside the bearing base and is configured to be driven by the knob to rotate. The guiding element includes a first gear and a second gear. The head belt set connects the body and the bearing base. The head belt set includes a first side head belt, a second side head belt, and an auxiliary head belt. The first gear is configured to drive the first side head belt and the second side head belt to move. The second gear is configured to drive the auxiliary head belt to move.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: April 28, 2020
    Assignees: STARVR CORPORATION, Acer Incorporated
    Inventors: Wei-Chih Wang, Kuan-Lin Chen, Yen-Chou Chueh, Hui-Ping Sun, Chun-Hsien Chen
  • Publication number: 20200126976
    Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Yu CHEN, Chih-Ping CHAO, Chun-Hung CHEN, Chung-Long CHANG, Kuan-Chi TSAI, Wei-Kung TSAI, Hsiang-Chi CHEN, Ching-Chung HSU, Cheng-Chang HSU, Yi-Sin WANG
  • Publication number: 20200127093
    Abstract: A method for manufacturing a semiconductor device includes following operations. A semiconductor substrate is received. A first semiconductive layer is formed over the semiconductor substrate. A plurality of dopants is formed in a first portion of the first semiconductive layer. A second portion of the first semiconductive layer is removed to form a patterned first semiconductive layer. A first sidewall profile of the first portion after the removing of the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion. An underneath layer is patterned to form a hole in the underneath layer using the patterned first semiconductive layer as a mask to pattern. A sidewall profile of the hole in the underneath layer is controlled by the first sidewall profile of the first portion of the first semiconductive layer.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: I-HSIU WANG, YEAN-ZHAW CHEN, YING-TING HSIA, JHAO-PING JIANG, CHUN-CHIH CHENG
  • Publication number: 20200098704
    Abstract: A method for fabricating a semiconductor structure is provided. The method includes forming a semiconductor chip; providing a printed circuit board; and forming an adhesive layer between a connection surface of the semiconductor chip and the printed circuit board to bond the semiconductor chip with the printed circuit board. The semiconductor chip includes a plurality of cutting tracks intersected with each other to enclose an area having corner regions. The connection surface of the semiconductor chip includes a plurality of conductive bumps and a plurality of first openings are formed in each of the corner regions.
    Type: Application
    Filed: November 27, 2019
    Publication date: March 26, 2020
    Inventors: Li Hui LU, Chun Chao FEI, Po Yuan CHIANG, Ya Ping WANG
  • Publication number: 20200073130
    Abstract: A head-mounted display includes a body, a bearing base, a knob, a guiding element, and a head belt set. The knob is pivoted to the bearing base and located outside the bearing base. The guiding element is pivoted to the bearing base and located inside the bearing base and is configured to be driven by the knob to rotate. The guiding element includes a first gear and a second gear. The head belt set connects the body and the bearing base. The head belt set includes a first side head belt, a second side head belt, and an auxiliary head belt. The first gear is configured to drive the first side head belt and the second side head belt to move. The second gear is configured to drive the auxiliary head belt to move.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 5, 2020
    Applicants: STARVR CORPORATION, Acer Incorporated
    Inventors: Wei-Chih Wang, Kuan-Lin Chen, Yen-Chou Chueh, Hui-Ping Sun, Chun-Hsien Chen
  • Publication number: 20200066902
    Abstract: The method comprises forming a drain region in the first layer. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 27, 2020
    Inventors: Tsai-Feng YANG, Chih-Heng SHEN, Chun-Yi YANG, Kun-Ming HUANG, Po-Tao CHU, Shen-Ping WANG
  • Publication number: 20200056882
    Abstract: A three-dimensional scanning system includes a projection light source, an image capturing apparatus, and a signal processing apparatus. The projection light source is configured to project a two-dimensional light to a target, where the two-dimensional light has a spatial frequency. The image capturing apparatus captures an image of the target illuminated with the two-dimensional light. The signal processing apparatus is coupled to the projection light source and the image capturing apparatus, to analyze a definition of the image of the two-dimensional light, where if the definition of the image of the two-dimensional light is lower than a requirement standard, the spatial frequency of the two-dimensional light is reduced.
    Type: Application
    Filed: December 27, 2018
    Publication date: February 20, 2020
    Inventors: Liang-Pin Yu, Yeong-Feng Wang, Chun-Di Chen, Yun-Ping Kuan
  • Patent number: 10559573
    Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: February 11, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Ru Wang, Ching-Cheng Lung, Yu-Tse Kuo, Chien-Hung Chen, Chun-Hsien Huang, Li-Ping Huang, Chun-Yen Tseng, Meng-Ping Chuang
  • Publication number: 20200042035
    Abstract: A head-mounted display includes a host, two installing bases, two connection elements and a head belt. The host has two installing grooves and two opposite sidewalls, and the two installing grooves respectively penetrate through the two sidewalls. The two installing bases are disposed in the host, wherein each installing base has an abutting portion and an installing portion connected to each other. The abutting portion of each installing base abuts against an inner edge of the corresponding sidewall, and the installing portion of each installing base is exposed outside of the host through the corresponding installing groove. The two connection elements are respectively installed onto the two installing portions of the two installing bases. The head belt has two opposite connection portions, and the two connection portions are respectively connected to the two connection elements.
    Type: Application
    Filed: January 30, 2019
    Publication date: February 6, 2020
    Applicants: STARVR CORPORATION, Acer Incorporated
    Inventors: Chun-Yu Chen, Ker-Wei Lin, Chun-Ta Chen, Hao-Ming Chang, Chun-Hsien Chen, Jen-Chieh Shih, Chih-Heng Tsou, Hui-Ping Sun, Wei-Chih Wang, Yen-Chou Chueh, Kuan-Lin Chen
  • Publication number: 20200035625
    Abstract: A package includes a semiconductor package including a semiconductor die and a first insulating encapsulation, a substrate, and a second insulating encapsulation. The first insulating encapsulation encapsulates the semiconductor die. The substrate includes a redistribution circuitry, wherein the substrate is electrically coupled to the semiconductor package through the redistribution circuitry. The second insulating encapsulation is disposed on and partially covers the substrate, wherein the substrate is sandwiched between the semiconductor package and the second insulating encapsulation.
    Type: Application
    Filed: May 24, 2019
    Publication date: January 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Publication number: 20200027803
    Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
  • Patent number: 10522479
    Abstract: A method for fabricating a semiconductor structure includes forming a semiconductor chip. Forming the semiconductor chip includes providing a substrate, forming a connection layer on the substrate, and forming a first passivation layer on the substrate. The first passivation layer contains a plurality of first openings to expose the connection layer. Forming the semiconductor chip also includes forming a plurality of second openings and a plurality of third openings in the second passivation layer. Each second opening is formed in a first opening to expose the connection layer, and each third opening is formed outside of the plurality of first openings to expose the first passivation layer. Further, forming the semiconductor chip includes forming a conductive bump in each second opening.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: December 31, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Li Hui Lu, Chun Chao Fei, Po Yuan Chiang, Ya Ping Wang
  • Patent number: D885383
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: May 26, 2020
    Assignees: STARVR CORPORATION, Acer Incorporated
    Inventors: Hao-Ming Chang, Ker-Wei Lin, Chun-Ta Chen, Chun-Yu Chen, Chun-Hsien Chen, Hui-Ping Sun, Wei-Chih Wang, Yen-Chou Chueh, Kuan-Lin Chen