Patents by Inventor Chun-Ping Wu

Chun-Ping Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10770313
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The first redistribution structure has a dielectric layer and a feed line disposed on the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The insulation encapsulation has a protrusion laterally wraps around the feed line. The insulation encapsulation has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The second redistribution structure is disposed on the die and the insulation encapsulation.
    Type: Grant
    Filed: April 21, 2019
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Chung-Hao Tsai, Chun-Lin Lu, Yen-Ping Wang, Che-Wei Hsu
  • Patent number: 10727082
    Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electric Magnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shou Zen Chang, Chun-Lin Lu, Kai-Chiang Wu, Ching-Feng Yang, Vincent Chen, Chuei-Tang Wang, Yen-Ping Wang, Hsien-Wei Chen, Wei-Ting Lin
  • Publication number: 20200168583
    Abstract: A semiconductor device includes a first semiconductor die package. The first semiconductor package includes a molding compound, and a conductive element in the molding compound, wherein a top surface of the conductive element is above or co-planar with a top-most surface of the molding compound. The semiconductor device further includes a second semiconductor die package The second semiconductor package includes a plurality of copper-containing contacts on a single metal pad, wherein each of the plurality of copper-containing contacts is bonded to the conductive element.
    Type: Application
    Filed: January 28, 2020
    Publication date: May 28, 2020
    Inventors: Yu-Feng CHEN, Chun-Hung LIN, Han-Ping PU, Ming-Da CHENG, Kai-Chiang WU
  • Publication number: 20200152570
    Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.
    Type: Application
    Filed: December 8, 2019
    Publication date: May 14, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Nan-Chin Chuang
  • Patent number: 10633118
    Abstract: A mobile rustproofing washing system includes a receptacle, a control module, a water supply module, a filtration module and a washing module. The receptacle is removably disposed on a mobile carrier. The control module is disposed in the receptacle. The water supply module is disposed in the receptacle and includes a front water tank and a rear water tank. The filtration module is connected to the front water tank and the rear water tank. The filtration module receives and filters water from the front water tank. The filtered water is stored in the rear water tank. The washing module connects with the rear water tank and receives water therefrom, so as to carry out a washing process. Therefore, the mobile rustproofing washing system is quick to mount/demount and easy to use, thereby having high mobility.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 28, 2020
    Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Yu-Ping Wang, Chin-Cheng Wu, Ming-Jia Wang, Chun-Yu Chen, Yi-Rong Zeng, Kuan-You Liu, Ming-Ta Hsieh, Ching-Wen Fan
  • Publication number: 20200118952
    Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.
    Type: Application
    Filed: December 15, 2019
    Publication date: April 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Nan-Chin Chuang
  • Publication number: 20200105675
    Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.
    Type: Application
    Filed: March 5, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Patent number: 10553561
    Abstract: A method of forming a semiconductor device includes preparing a first semiconductor die package with conductive elements embedded in a molding compound, wherein the conductive elements are exposed on a surface of the molding compound. A top surface of the conductive elements is above or co-planar with a top-most surface of the molding compound. The method further includes providing a second semiconductor die package; and bonding the conductive elements of the first semiconductor die package to contacts on the semiconductor die package.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Feng Chen, Chun-Hung Lin, Han-Ping Pu, Ming-Da Cheng, Kai-Chiang Wu
  • Patent number: 10553533
    Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Nan-Chin Chuang
  • Publication number: 20200035625
    Abstract: A package includes a semiconductor package including a semiconductor die and a first insulating encapsulation, a substrate, and a second insulating encapsulation. The first insulating encapsulation encapsulates the semiconductor die. The substrate includes a redistribution circuitry, wherein the substrate is electrically coupled to the semiconductor package through the redistribution circuitry. The second insulating encapsulation is disposed on and partially covers the substrate, wherein the substrate is sandwiched between the semiconductor package and the second insulating encapsulation.
    Type: Application
    Filed: May 24, 2019
    Publication date: January 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Publication number: 20200027803
    Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
  • Patent number: 10522437
    Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
  • Patent number: 10510693
    Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Nan-Chin Chuang
  • Patent number: 10381309
    Abstract: A package structure includes a first redistribution layer, a second redistribution layer, at least one semiconductor chip, an insulating encapsulation, a protection layer, and at least one connecting module. The at least one semiconductor chip is located between and electrically connected to the first redistribution layer and the second redistribution layer. The insulating encapsulation encapsulates the at least one semiconductor chip. The protection layer is disposed on and partially covers the first redistribution layer, wherein the first redistribution layer is located between the at least one semiconductor chip and the protection layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 13, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Kai-Chiang Wu, Albert Wan
  • Publication number: 20190244834
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The first redistribution structure has a dielectric layer and a feed line disposed on the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The insulation encapsulation has a protrusion laterally wraps around the feed line. The insulation encapsulation has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The second redistribution structure is disposed on the die and the insulation encapsulation.
    Type: Application
    Filed: April 21, 2019
    Publication date: August 8, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Chung-Hao Tsai, Chun-Lin Lu, Yen-Ping Wang, Che-Wei Hsu
  • Patent number: 10322436
    Abstract: A method of applying a riblet structure coating on the internal surface of a pipe includes coating the internal surface of a pipe with a resin layer and applying a cavity mold having a reverse riblet pattern structure to the coated internal surface of the pipe. A flexible air bag is inserted into the interior of the pipe and charged with air to hold the mold against the coated internal surface of the pipe. The air bag may be charged with air for a sufficient amount of time to allow the coating to cure in the riblet shape of the mold. Afterwards, the air bag and the mold are removed from the pipe to yield a pipe coated with an internal riblet structure.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: June 18, 2019
    Assignee: NANO AND ADVANCED MATERIALS INSTITUTE LIMITED
    Inventors: Su Ping Bao, Lei Gao, Man Lung Sham, Chun Ping Wu, Chi Wai Li
  • Publication number: 20190157206
    Abstract: A package structure includes a first redistribution layer, a second redistribution layer, at least one semiconductor chip, an insulating encapsulation, a protection layer, and at least one connecting module. The at least one semiconductor chip is located between and electrically connected to the first redistribution layer and the second redistribution layer. The insulating encapsulation encapsulates the at least one semiconductor chip. The protection layer is disposed on and partially covers the first redistribution layer, wherein the first redistribution layer is located between the at least one semiconductor chip and the protection layer.
    Type: Application
    Filed: April 30, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Kai-Chiang Wu, Albert Wan
  • Publication number: 20190139890
    Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.
    Type: Application
    Filed: April 30, 2018
    Publication date: May 9, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Nan-Chin Chuang
  • Publication number: 20180099312
    Abstract: A method of applying a riblet structure coating on the internal surface of a pipe includes coating the internal surface of a pipe with a resin layer and applying a cavity mold having a reverse riblet pattern structure to the coated internal surface of the pipe. A flexible air bag is inserted into the interior of the pipe and charged with air to hold the mold against the coated internal surface of the pipe. The air bag may be charged with air for a sufficient amount of time to allow the coating to cure in the riblet shape of the mold. Afterwards, the air bag and the mold are removed from the pipe to yield a pipe coated with an internal riblet structure.
    Type: Application
    Filed: October 6, 2017
    Publication date: April 12, 2018
    Inventors: Su Ping BAO, Lei GAO, Man Lung SHAM, Chun Ping WU, Chi Wai LI
  • Publication number: 20070159340
    Abstract: A structure for packaging a radio frequency identification (RFID) device is disclosed, which comprises a substrate, an antenna formed on the substrate, a RFID chip with a first side attached to the substrate and a second side having at least one signal pin exposed, at least one conductive contact plate placed on the substrate in contact with both the exposed signal pin and a portion of the antenna, and a protective film over the contact plate to secure the same to the substrate, wherein an electrical connection between the signal pin and the portion of the antenna is made through the contact plate.
    Type: Application
    Filed: January 9, 2007
    Publication date: July 12, 2007
    Inventors: Kuo-Tung Chiang, Shun-Chi Chang, Chun-Ping Wu, Mei-Yi Wu, Cheng-Hsien Chou, Mong-Tai Yang, Min Wu