Abstract: A column start signal generation circuit for a memory device, comprising a dummy data storage unit including a plurality of dummy cells for storing dummy data, each of the plurality of dummy cells being connected to a corresponding one of a plurality of word lines and a first dummy bit line or a second dummy bit line, the second dummy bit line being complementary to the first dummy bit line, a dummy data generator for outputting the dummy data to the plurality of dummy cells in the dummy data storage unit in response to a state of a write signal inputted therein, a sense amplification circuit for amplifying the dummy data from one of the plurality of dummy cells in the dummy data storage unit connected to an enabled one of the plurality of word lines, and a sense amplification sensor for sensing a level of an output signal from the sense amplification circuit and outputting a column start signal in accordance with the sensed result.