Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure, which has an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure, is formed, a cover layer is formed over the fin structure, a thermal operation is performed on the fin structure covered by the cover layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper fin structure. The thermal operation changes a germanium distribution in the upper fin structure.

Abstract: A light-emitting device includes a substrate, a semiconductor epitaxial structure, and an etch stop layer. The substrate has a first surface and a second surface opposite to the first surface. The semiconductor epitaxial structure has a side surface that has a roughened structure formed with protrusions, and includes a first type semiconductor layer, an active layer, and a second type semiconductor layer disposed on the first surface of the substrate in such order. The etch stop layer is disposed on a surface of the semiconductor epitaxial structure away from the substrate for preventing an etching solution from etching the semiconductor epitaxial structure. A light-emitting package and a light-emitting apparatus are also provided. A method for manufacturing a light-emitting device is also provided.

Abstract: A flat-top beam generating system may include a beamsplitting apparatus including one or more beamsplitters to split an input beam into three or more sub-beams that propagate along optical paths with different optical path lengths. The system may further include a diffractive optical element (DOE) to diffract the three or more sub-beams into a plurality of diffracted sub-beams. The system may further include one or more optical elements configured to collect the plurality of diffracted sub-beams to provide a flat-top beam.

Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

Abstract: An atomization device and a method of predicting atomization time for the same are provided. The atomization device includes a control module, an atomization module and a breathing sensing module. The method includes: configuring the breath sensing module to detect inhalations of a user using the atomization device, so as to generate initial breath data correspondingly; and configuring the control module to perform: comparing inhalation data of the initial breath data with a valid inhalation standard to obtain valid inhalation data and filter noise; statistically analyzing the valid inhalation data to generate a predicted value of inhalation time; calculating an atomization time according to the predicted value of the inhalation time; and generating a driving signal to drive the atomization module to perform atomization according to the atomization time.

Abstract: A method of moving a susceptor in a processing system, suitable for use in semiconductor processing, is provided. The method includes: moving a first susceptor from an interior volume of a first enclosure to an interior volume of a process chamber during a first time period; and positioning, during a second time period, a first substrate on the first susceptor when the first susceptor is in the process chamber, wherein the interior volume of the first enclosure and interior volume of the process chamber are maintained at a non-atmospheric pressure from the beginning of the first time period until the end of the second time period.

Abstract: A near-field communication (NFC) antenna system comprising an antenna, a plurality of chips, and an antenna matching network connected on one side to the plurality of chips and on another side to the antenna. Wherein only one of the plurality of chips is active at a time with inactive chips have an impedance set combined with the antenna matching network to provide antenna matching with the active chip. The NFC antenna inactive chips are set to open having a corresponding impedance and the impedance is set based on any of transmission line length, width, and gap between. The plurality of chips includes a charging chip and a payment chip.

Abstract: A modified cutinase is disclosed. The cutinase has the modified amino acid sequence of SEQ ID NO: 2, wherein the modification is a substitution of asparagine at position 181 with alanine, or substitutions of asparagine at position 181 with alanine and phenylalanine at position 235 with leucine. The modified enzyme has improved PET-hydrolytic activity, and thus, the high-activity PET hydrolase is obtained, and the industrial application value of the PET hydrolase is enhanced.

Abstract: Devices, such as transistors, that use bismuth to create ohmic contacts are provided, as are methods of manufacturing the same. The transistors, such as field-effect transistors, can include one or more two-dimensional materials, and electrical contact areas can be created on the two-dimensional material(s) using bismuth. The bismuth can help to provide energy-barrier free, ohmic contacts, and the resulting devices can have performance levels that rival or exceed state-of-the-art devices that utilize three-dimensional materials, like silicon. The two-dimensional materials can include transition metal dichalcogenides, such as molybdenum disulfide.

Abstract: A wafer container includes a frame, a door and at least a pair of shelves. The frame has opposite sidewalls. The pair of the shelves are respectively disposed and aligned on the opposite sidewalls of the frame. Various methods and devices are provided for holding at least one wafer to the shelves during transport.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. The epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. A lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer.

Abstract: A semiconductor wafer processing system includes a stocker having an interior surface, a wafer carrier disposed within the stocker, a wafer shelf disposed within the wafer carrier for storing a semiconductor wafer, and a discharge circuit including a first conductor electrically coupled to the wafer shelf and a first current controller electrically coupled to the first conductor and to the interior surface of the stocker.

Abstract: A heat conduction device with an inner loop includes a vapor chamber having at least one hole edge and a heat pipe having an outer pipe and an inner pipe. The outer pipe has a closed end and an open end communicating with the hole edge. Two ends of the inner pipe are open. The inner pipe has one end communicating with the vapor chamber through the hole edge and the other end extended along the axial direction of the outer pipe to form at least one port for communicating the closed end of the outer pipe with the inner pipe. The inner pipe is located inside the outer pipe to form a gap annularly. The port communicates with the gap, so that the inner loop is formed between the vapor chamber and the heat pipe.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a channel structure over a substrate and forming a dielectric layer over the channel structure. The dielectric layer has a higher dielectric constant greater than silicon nitride. The method also includes forming a gate stack over the dielectric layer and forming a spacer element over a sidewall of the gate stack. The spacer element covers a portion of the dielectric layer.

Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.

Abstract: A method for preparing a fermented food by using a Rhizopus microsporus strain is provided. The method includes the following steps: providing an isolated and purified Rhizopus microsporus strain, and its deposit number is DSM 34400; and inoculating the isolated and purified Rhizopus microsporus strain to a substrate for fermentation to form a fermented food. The substrate includes a legume, a processing residue of a legume, or a combination thereof.

Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.

Abstract: In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.

Abstract: A portable electronic charging case, with a compact form-factor, such as for a smart ring or the like, includes a base; a front cover connected to the base and configured to seal an interior of the charging case; a post on the base and in the interior; an antenna disposed within the post; and circuitry connected to the antenna and to a charging port located on the base. The electronic charging case includes advanced functionality, an aesthetic design, and a compact form-factor. The compact form-factor includes an embedded battery, an environmentally sealed design, and a small NFC/Bluetooth antenna. The aesthetic design includes no user-actuated mechanisms on an exterior of the charging case and an intelligent light sensor for illuminating the charging case. The advanced functionality includes the embedded battery, intelligent light sensor, a temperature sensor for monitoring a user, and monitoring techniques working in conjunction with an associated wearable device.