Abstract: In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.

Abstract: A light-emitting diode (LED) includes a substrate, an epitaxial structure, and an electrode structure. The epitaxial structure includes a first semiconductor layer, an active layer and a second semiconductor layer that are sequentially disposed on the substrate in such order. The electrode structure includes electrodes that are respectively disposed on the first and second semiconductor layers opposite to the substrate. Each electrode has an upper surface that is opposite to the first and second semiconductor layers. The electrode structure also includes an insulating unit that is disposed in each electrode, and that is not exposed from the upper surface of the corresponding electrode.

Abstract: The present invention relates to a preparation method of biobased adipic acid. In the method, by using a nickel-based hydrogenation catalyst provided by the present invention, when a substrate concentration is as high as 200 g/L, the reaction of biobased sodium muconate and hydrogen is catalyzed in a batch reactor and a micro packed bed to prepare sodium adipate, and the yield of a target product is close to 100 mol %. Wherein the biobased sodium muconate is biobased sodium muconate obtained by microbial fermentation. The method has the advantages of short reaction path, good economy, and easy large-scale preparation, and lays a solid foundation for the industrialization of green synthesis of the biobased adipic acid.

Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.

Abstract: In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.

Abstract: A data storage device includes a substrate including a number of contact pads and a number of passive component packages coupled to the contact pads. The data storage device further includes a memory controller coupled to the substrate, and one or more NAND die stacks coupled to the substrate and in electrical communication with the memory controller. One or more of the passive component packages include a first passive component, a second passive component electrically connected to the first passive component, and a first terminal coupled to the first passive component. The passive component packages further include a second terminal coupled to the second passive component, and a third terminal coupled to a common node of the first passive component and the second passive component.

Abstract: A semiconductor structure including a pillar structure and a spacer structure is provided. The pillar structure is disposed over a substrate, and comprises: a lower layer, disposed on the substrate; an upper layer, disposed over the lower layer; and a dielectric layer, disposed between the lower layer and the upper layer, wherein the upper layer includes a first portion and a second portion disposed below and connecting the first portion. The spacer structure laterally surrounds the pillar structure, and comprises: an upper portion, surrounding the first portion of the upper layer; and a lower portion, disposed below and connecting the upper portion, wherein a first thickness of the upper portion is substantially greater than a second thickness of the lower portion. A method for manufacturing a semiconductor structure is also provided.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes first semiconductor channel layers, second semiconductor channel layers, a dielectric wall, a gate structure, a source/drain electrode and an inner spacer. The first semiconductor channel layers are stacked vertically apart along a first direction over a substrate. The second semiconductor channel layers are stacked vertically apart along the first direction over the substrate. The dielectric wall is disposed between and separates the first semiconductor channel layers and the second first semiconductor channel layers, wherein the dielectric wall comprises a liner and a dielectric wall material disposed over the liner. The gate structure extends along a second direction perpendicular to the first direction disposed crossing over a channel region of the first fin structure and a channel region of the second fin structure. The source/drain electrode is in contact with the first semiconductor channel layers.

Abstract: A method for inter-radio access technology (inter-RAT) handover includes establishing New Radio (NR) connection between user equipment (UE) and a network, sending first Measurement Report by the UE to the network when one of following conditions occurs: New Radio (NR) signal quality does not satisfy an NR signal threshold, Real-time Transport Protocol (RTP) measurement does not satisfy an RTP threshold, and the UE changes a calling preference to voice over Wi-Fi (VoWiFi). The method further includes triggering a handover from VoNR to voice over LTE (VoLTE) by the network, and triggering a handover from VoLTE to VoWiFi by the UE.

Abstract: Disclosed is a charger for a smart ring that includes a charger island disposed to the charger and configured to receive the smart ring. The charger island has a plurality of transmit antennas located in or on the charger island. When activated, a transmit antenna is configured to couple, via a Near Field Communication (NFC) chip/circuit, with a receive antenna on the smart ring for charging thereof. The active transmit antenna is based on an orientation of the smart ring on the charger island where the charging is performed regardless of alignment between the ring and the charger island. A conductive sheet can be included between the plurality of transmit antennas and an interior of the charger island in order to isolate the plurality of transmit antennas from one another.

Abstract: A semiconductor wafer processing system includes a stocker having an interior surface, a wafer carrier disposed within the stocker, a wafer shelf disposed within the wafer carrier for storing a semiconductor wafer, and a discharge circuit including a first conductor electrically coupled to the wafer shelf and a first current controller electrically coupled to the first conductor and to the interior surface of the stocker.

Abstract: A reaction apparatus is provided. The reaction apparatus includes a first tank, a second tank, a cover, a stirring assembly, a heater, a controller and a gas delivery system. The first tank has an accommodating space. The second tank is in the accommodating space of the first tank and includes holes. The cover is on an opening of the first tank. The stirring assembly is on the cover. The stirring assembly includes a driving motor and a stirrer connected to the driving motor. The stirrer is in the accommodating space of the first tank. The heater is in the accommodating space of the first tank. The controller is coupled to the heater to control the heater. The gas delivery system is on the first tank and in communication with the accommodating space of the first tank.

Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.

Abstract: A method for preparing quartz glass with low content of hydroxyl and high purity, includes providing silica powders including hydroxyl groups. The silica powders are dehydroxylated, which includes drying the silica powders at a first temperature, heating the silica powders up to a second temperature and introducing a first oxidizing gas including halogen gas, thereby obtaining first dehydroxylated powders, and heating the first dehydroxylated powders up to a third temperature and introducing a second oxidizing gas including oxygen or ozone, thereby obtaining second dehydroxylated powders. The second dehydroxylated powders are heated up to a fourth temperature to obtain a vitrified body. The vitrified body is cooled to obtain the quartz glass with low content of hydroxyl and high purity. The quartz glass prepared by the above method has low content of hydroxyl and high purity. A quartz glass with low content of hydroxyl and high purity is also provided.

Abstract: A semiconductor device includes a first semiconductor structure, a second semiconductor structure, a first isolation block and a second isolation block. The first semiconductor structure includes a first gate structure wrapping around a first sheet structures and a second sheet structures, and a first dielectric wall disposed between and separating the first and second sheet structures. The second semiconductor structure includes a second gate structure wrapping around third sheet structures. The first isolation block is disposed on the first dielectric wall of the first semiconductor structure and separates the first gate structure into a first gate portion wrapping around the first sheet structures and a second gate portion wrapping around the second sheet structures. The second isolation block is disposed between the first and second semiconductor structures and separates the first gate structure from the second gate structure.

Abstract: A flat-top beam generating system may include a beamsplitting apparatus including one or more beamsplitters to split an input beam into three or more sub-beams that propagate along optical paths with different optical path lengths. The system may further include a diffractive optical element (DOE) to diffract the three or more sub-beams into a plurality of diffracted sub-beams. The system may further include one or more optical elements configured to collect the plurality of diffracted sub-beams to provide a flat-top beam.

Abstract: A near-field communication (NFC) antenna system comprising an antenna, a plurality of chips, and an antenna matching network connected on one side to the plurality of chips and on another side to the antenna. Wherein only one of the plurality of chips is active at a time with inactive chips have an impedance set combined with the antenna matching network to provide antenna matching with the active chip. The NFC antenna inactive chips are set to open having a corresponding impedance and the impedance is set based on any of transmission line length, width, and gap between. The plurality of chips includes a charging chip and a payment chip.