Abstract: A semiconductor structure includes a substrate, word lines, bit line contact plugs, and first isolation layers. The word lines are located in the substrate. A bit line contact hole is provided between two adjacent word lines. The bit line contact plugs are located in the bit line contact holes. The first isolation layers are located on side walls of the bit line contact holes and cover side walls of the bit line contact plugs.

Abstract: The present application provides a memory and a manufacturing method thereof, and relates to the field of semiconductor technologies. The memory includes a substrate, the substrate is provided with a control region, and two sides of the control region are respectively provided with storage regions; each of the storage regions includes multiple rows of first active regions, and all the first contact regions in each row of the first active regions are connected by a bit line; the control region includes multiple second active regions, each of the second active regions is provided with a first gate and a first source/drain region and a second source/drain region that are located on two sides of the first gate, and all the first gates in the control region are connected with each other to form a control line; the first source/drain region and the second source/drain region in a same second active region are respectively connected with a corresponding bit line.

Abstract: A semiconductor structure includes a substrate, word lines, bit line contact plugs, and first isolation layers. The word lines are located in the substrate. A bit line contact hole is provided between two adjacent word lines. The bit line contact plugs are located in the bit line contact holes. The first isolation layers are located on side walls of the bit line contact holes and cover side walls of the bit line contact plugs.