Abstract: This invention discloses sustainable DRAM with principle power supply voltage which is unified with an external logic circuit. The DRAM circuit is configured to couple with the external logic circuit and with a principle power supply voltage source. The DRAM circuit comprises a first sustaining voltage generator and a DRAM core circuit. The first sustaining voltage generator generates a first voltage level which is higher than a voltage level corresponding to a signal ONE utilized in the DRAM circuit. The DRAM core circuit has a DRAM cell comprising an access transistor and a storage capacitor, and the storage capacitor of the DRAM cell is configured to selectively coupled to the first sustaining voltage generator. Wherein, a voltage level of the principle power supply voltage source to the DRAM circuit is the same or substantially the same as that of a principle power supply voltage source to the external logic circuit.

Abstract: A memory chip includes a plurality of memory banks, an I/O data bus, and a plurality of align circuits. Each memory bank outputs or receives a data set in parallel. The plurality of align circuits correspond to the plurality of memory banks respectively. The data set of one memory bank is transferred to one corresponding align circuit which then simultaneously transfers the data set to the I/O data bus in parallel, or the data set is transferred from the I/O data bus to the one corresponding align circuit which then simultaneously transfers the data set to the one memory bank in parallel. There is no parallel-to-serial circuit and serial-to-parallel circuit between the I/O data bus and each memory banks.

Abstract: A DRAM structure includes a semiconductor substrate, a plurality of DRAM cells, a Bitline, a sense amplifier, and a local wordline. The semiconductor substrate has a top surface. Each DRAM cell includes an access transistor and a storage capacitor. The Bitline has a first terminal extended along the plurality of DRAM cells to a second terminal, and the Bitline is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the Bitline. The local wordline is connected to a gate terminal of the access transistor of a first DRAM cell in the plurality of DRAM cells. A refresh cycle time, a write cycle time, or a read cycle time of the DRAM structure is less than 5 ns.

Abstract: A hybrid memory chip as well as a memory system and a computing apparatus including the hybrid memory chip are provided. The hybrid memory chip includes: dynamic random access memory (DRAM) arrays; sense amplifier arrays, disposed around each of the DRAM arrays; and static random access memory (SRAM) arrays, disposed around each of the DRAM arrays, and respectively abutted with one of the sense amplifier arrays. The sense amplifier arrays are configured to perform read operations from the DRAM arrays and the SRAM arrays. Bit lines across the DRAM arrays extend through the sense amplifier arrays and the SRAM arrays.

Abstract: A memory device is provided. The memory device includes: a package substrate; a memory chip, with chip inputs/outputs (I/Os), and attached to the package substrate; and package terminals, disposed on the package substrate, and having: functional package terminals, connected to the chip I/Os; no-connect (NC) package terminals, arranged among the functional package terminals and not connected to any of the chip I/Os; and redesigned NC package terminals, as additional ones of the NC package terminals but connected to the chip I/Os, so as to be functioned as additional functional package terminals.

Abstract: An integrated circuit includes a semiconductor substrate, a P type metal-oxide-semiconductor (PMOS) transistor, an N type guard ring, an N type metal-oxide-semiconductor (NMOS) transistor, a P type guard ring, and a first interconnection layer. The semiconductor substrate has an original surface. The P type metal-oxide-semiconductor (PMOS) transistor includes a gate node, a source node, and a drain node. The N type guard ring surrounds the PMOS transistor. The N type metal-oxide-semiconductor (NMOS) transistor includes a gate node, a source node, and a drain node. The P type guard ring surrounds the NMOS transistor. The first interconnection layer is under the original surface of the semiconductor substrate and isolated from the semiconductor substrate. The first interconnection layer is electrically connected to the PMOS transistor, the N type guard ring, the NMOS transistor, or the P type guard ring.

Abstract: A memory array circuit includes a semiconductor substrate, a bitline, a complementary bitline, and a bitline sense amplifier circuit, wherein the bitline sense amplifier circuit includes a first plurality of transistors and a first set of connection lines. The semiconductor substrate has an original surface. The bitline sense amplifier circuit is connected to the bitline and the complementary bitline. Each transistor includes a gate node, a first conductive node, and a second conductive node. The first set of connection lines connects the first conductive nodes of the first plurality of transistors to the bitline and the complementary bitline. The first set of connection lines are under the original surface of the semiconductor substrate.

Abstract: A semiconductor device package is provided. The semiconductor device package comprises a first electronic component, a second electronic component above the first electronic component and an interconnection structure disposed external to both the first electronic component and the second electronic component and configured to electrically connect the first electronic component to the second electronic component, a package material configured to hold the first electronic component and the second electronic component together and an external connector configured to electrically connect the first and second electronic components to an external device. The first electronic component has a portion free from being covered by the second electronic component. The external connector is positioned directly above the portion of the first electronic component.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.

Abstract: A memory device is provided. The memory device includes: a latch circuit, having a first inverter and a second inverter cross-coupled with each other, wherein a first pull up transistor and a first pull down transistor of the first inverter are coupled through a first selection transistor, and a second pull up transistor and a second pull down transistor of the second inverter are coupled through a second selection transistor; a first access transistor, coupled to a first storage node of the latch circuit; and a second access transistor, coupled to a second storage node of the latch circuit.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.

Abstract: A memory chip includes a memory bank, I/O data bus, and a first plurality of sensing amplifiers. The first plurality of sensing amplifiers are between the memory bank and the I/O data bus and configured to output a first plurality of data in parallel to the I/O data bus. There is no parallel-to-serial circuit and no serial-to-parallel circuit in the memory chip.

Abstract: A memory array circuit includes a semiconductor substrate, a bit line, a complementary bit line, and a bit line sense amplifier circuit. The semiconductor substrate has an original surface. The bit line sense amplifier circuit is connected to the bit line and the complementary bit line, and the bit line sense amplifier circuit includes a first plurality of transistors and a first set of connection lines. Each transistor includes a gate node, a first conductive node, and a second conductive node. The first set of connection lines connects the first plurality of transistors to the bit line and the complementary bit line; wherein the first set of connection lines is above the original surface of the semiconductor substrate, and the bit line and the complementary bit line are under the original surface of the semiconductor substrate.

Abstract: A semiconductor memory structure includes a semiconductor substrate, a plurality of DRAM (dynamic random access memory) cells, a bit line, a sense amplifier, and a local word line. The semiconductor substrate has a top surface. Each DRAM cell includes an access transistor and a storage capacitor. The bit line has a first terminal extended along the plurality of DRAM cells to a second terminal, and the bit line is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the bit line. The local word line is connected to a gate conductive region of an access transistor of a first DRAM cell in the plurality of DRAM cells. A rising time or a falling time of a voltage signal in the local word line is less than 4 ns.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

Abstract: A memory system comprises a memory and a physical layer circuit. The memory system comprises a memory, a data bus and a single-pin STB. The memory receives a parallel command though the data bus, and receives a serial command through the STB. The physical layer circuit is configured to transmit the parallel command to the data bus. The physical layer circuit is configured to convert STB input data from the controller into the serial command and transmit the serial command to the STB.

Abstract: The invention provides a memory module, comprising a first memory die with a first surface and a third surface opposite to the first surface, wherein a first redistribution layer and a first original pad set are formed over the first surface; a second memory die with a second surface and a fourth surface opposite to the second surface, wherein a second original pad set are formed over the second surface; a wire bonding pad set disposed over the first surface, wherein the wire bonding pad set are electrically connected with the first original pad set; and a plurality of wires bonded to the wire bonding pad set, wherein the first memory die is bonded to the second memory die, the first surface faces the second surface, and the second original pad set are electrically connected with the wire bonding pad set.

Abstract: A memory controller includes a command processor. When an access command is performed by the memory controller, the command processor generates a row address information to the memory before issuing an active command to the memory. The row address information and the active command are issued by the command processor based on the access command.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.