Abstract: A semiconductor memory structure includes a semiconductor substrate, a plurality of DRAM (dynamic random access memory) cells, a bit line, a sense amplifier, and a local word line. The semiconductor substrate has a top surface. Each DRAM cell includes an access transistor and a storage capacitor. The bit line has a first terminal extended along the plurality of DRAM cells to a second terminal, and the bit line is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the bit line. The local word line is connected to a gate conductive region of an access transistor of a first DRAM cell in the plurality of DRAM cells. A rising time or a falling time of a voltage signal in the local word line is less than 4 ns.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

Abstract: A memory system comprises a memory and a physical layer circuit. The memory system comprises a memory, a data bus and a single-pin STB. The memory receives a parallel command though the data bus, and receives a serial command through the STB. The physical layer circuit is configured to transmit the parallel command to the data bus. The physical layer circuit is configured to convert STB input data from the controller into the serial command and transmit the serial command to the STB.

Abstract: The invention provides a memory module, comprising a first memory die with a first surface and a third surface opposite to the first surface, wherein a first redistribution layer and a first original pad set are formed over the first surface; a second memory die with a second surface and a fourth surface opposite to the second surface, wherein a second original pad set are formed over the second surface; a wire bonding pad set disposed over the first surface, wherein the wire bonding pad set are electrically connected with the first original pad set; and a plurality of wires bonded to the wire bonding pad set, wherein the first memory die is bonded to the second memory die, the first surface faces the second surface, and the second original pad set are electrically connected with the wire bonding pad set.

Abstract: A memory controller includes a command processor. When an access command is performed by the memory controller, the command processor generates a row address information to the memory before issuing an active command to the memory. The row address information and the active command are issued by the command processor based on the access command.

Abstract: The present invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word line coupled to a gate terminal of the access transistor. During the period between the word line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.

Abstract: A memory system comprises a memory and a physical layer circuit. The memory system comprises a memory, a data bus and a single-pin STB. The memory receives a parallel command though the data bus, and receives a serial command through the STB. The physical layer circuit is configured to transmit the parallel command to the data bus. The physical layer circuit is configured to convert STB input data from the controller into the serial command and transmit the serial command to the STB.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

Abstract: A memory controller includes a command processor. When an access command is performed by the memory controller, the command processor generates a column address information to the memory between issuing an active command to the memory and issuing a read or write command to the memory. The column address information and the active command are issued by the command processor based on the access command.

Abstract: This invention discloses sustainable DRAM with principle power supply voltage which is unified with an external logic circuit. The DRAM circuit is configured to couple with the external logic circuit and with a principle power supply voltage source. The DRAM circuit comprises a first sustaining voltage generator and a DRAM core circuit. The first sustaining voltage generator generates a first voltage level which is higher than a voltage level corresponding to a signal ONE utilized in the DRAM circuit. The DRAM core circuit has a DRAM cell comprising an access transistor and a storage capacitor, and the storage capacitor of the DRAM cell is configured to selectively coupled to the first sustaining voltage generator. Wherein, a voltage level of the principle power supply voltage source to the DRAM circuit is the same or substantially the same as that of a principle power supply voltage source to the external logic circuit.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

Abstract: A memory controller includes a command processor. When an access command is performed by the memory controller, the command processor generates a row address information to the memory before issuing an active command to the memory. The row address information and the active command are issued by the command processor based on the access command.

Abstract: A memory chip includes a memory bank, an I/O data bus, and a first plurality of sensing amplifiers. The first plurality of sensing amplifiers is configured to parallelly output a first plurality of data. A width of the I/O data bus is equal to a width of the first plurality of data parallelly outputted by the first plurality of sensing amplifiers.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

Abstract: A memory circuit includes a plurality of banks and a controller, each bank of the plurality of banks includes a plurality of segments, and each segment of the plurality of segments includes a plurality of bit lines and a plurality of word lines. A word line switch corresponding to a word line of a segment of the memory circuit is turned on and data are written into memory cells of the segment coupled to a plurality of bit lines of the segment and corresponding to the word line in turn after the controller enables an active command corresponding to the word line. When the controller enables at least one copy row write command, the data are simultaneously written into memory cells sharing a plurality of sense amplifiers with the plurality of bit lines of the segment and corresponding to at least one another word line.

Abstract: A memory circuit capable of being quickly written in data includes a plurality of banks, and each bank of the plurality of banks includes a plurality of segments. Each segment of the plurality of segments includes a plurality of bit line groups, and each bit line group of the plurality of bit line groups corresponds to a pre-charge line. When a predetermined signal is enabled, a potential is written into memory cells of the each segment corresponding to the each bit line group through the pre-charge line and the each bit line group.

Abstract: A circuit for outputting information of a memory circuit during a self-refresh mode includes a driver. The driver is coupled to a self-refresh control circuit and a self-refresh address counter. The driver is used for driving a plurality of pads of the memory circuit to output information of a plurality of inner signals corresponding to a self-refresh mode signal, and output information of addresses of a plurality of word lines of the memory circuit when the self-refresh mode signal and a test mode signal are enabled and the memory circuit enters the self-refresh mode. Each word line of the plurality of word lines corresponds to an inner signal of the plurality of inner signals.

Abstract: A circuit for outputting information of a memory circuit during a self-refresh mode includes a driver. The driver is coupled to a self-refresh control circuit and a self-refresh address counter. The driver is used for driving a plurality of pads of the memory circuit to output information of a plurality of inner signals corresponding to a self-refresh mode signal, and output information of addresses of a plurality of word lines of the memory circuit when the self-refresh mode signal and a test mode signal are enabled and the memory circuit enters the self-refresh mode. Each word line of the plurality of word lines corresponds to an inner signal of the plurality of inner signals.