Abstract: An apparatus can include a block program erase count (PEC) component. The block PEC component can monitor a quantity of program erase counts (PECs) for each particular type of block of a non-volatile memory array. The block PEC component can further determine which block of the superblock to write host data to next based on the quantity of PECs. The block PEC component can further write host data to the determined block.

Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a program-erase cycle count associated with at least a portion of the plurality of memory cells. The processing device is further to erase, based on the value of the PEC count, less than a predetermined portion of free sets of memory cells to form an erased set of memory cells. The processing device is further to receive a programming command directed to at least a portion of the erased set of memory cells. The processing device is further to perform a programming operation with respect to the at least a portion of the erased set of memory cells.

Abstract: Methods, systems, and devices for techniques for retiring blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. Upon determining the occurrence of the error, the memory system may identify one or more operating conditions associated with the block. For example, the memory system may determine a temperature of the block, a cycle count of the block, a quantity of times the block has experienced an error, a bit error rate of the block, and/or a quantity of available blocks in the associated system. Depending on whether a criteria associated with a respective operating condition is satisfied, the block may be enabled or retired.

Abstract: A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.

Abstract: A memory sub-system causing execution of a first wordline leakage test of a first wordline group of a set of wordline groups of a memory block in response to determining a temperature of the memory block is within a threshold temperature range. A first result of the first wordline leakage test is determined. A second wordline leakage test of a second wordline group is caused to be executed and a second result is determined. A determination is made that the first result of the first wordline leakage test of the first wordline group satisfies a first condition. A determination is made that the second result of the second wordline leakage test of the second wordline group satisfies a second condition. In response to satisfaction of the conditions, an action is executed.

Abstract: Aspects of the present disclosure are directed to a memory sub-system using a block family error avoidance (BFEA) scan to adjust read voltages. Three-level cell (TLC) memory stores three bits per cell. Due to variances in manufacturing and degradation over time, the actual voltages stored in the memory cells deviate from the target voltages. As a result, the comparisons between the read voltages and the stored voltages may generate erroneous results. A BFEA scan may be based on a single wordline and single page type. However, determining a single threshold voltage shift to apply to all read voltages may not compensate for all causes of voltage shifting. Accordingly, a BFEA scan may use multiple wordlines (e.g., one for each page) and determine different voltage offset values for each page. As a result, the accuracy of the read voltage applied is increased and the bit error rate (BER) is reduced.

Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

Abstract: Methods, systems, and devices for efficient read disturb scanning are described. A memory system may limit a quantity of word lines scanned as part of a read disturb scan. For example, the memory system may select a threshold quantity of word lines of a block for the read disturb scan based on a characterization of the word lines, such as selecting one or more word lines having higher bit error rates than other word lines of the block. The memory system may perform the read disturb scan on the selected one or more word lines to determine respective failure bit counts of the selected word lines and exclude unselected word lines of the block from the read disturb scan. The memory system may determine whether to perform a refresh operation on the block based on whether a respective failure bit count satisfies a threshold failure bit count.

Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a metric associated with the memory array. Responsive to determine that the value of the metric is below a predetermined threshold, the processing device is further to initiate an erase protocol of the memory device. The processing device is further to erase sets of memory cells associated with one or more memory blocks of the memory array. The processing device is further to receive a programming command directed to the first set of memory cells. The processing device is further to perform a programming operation with respect to a set of memory cells responsive to receiving the programming command.

Abstract: An apparatus can include a block program erase count (PEC) component. The block PEC component can monitor a quantity of program erase counts (PECs) for each particular type of block of a non-volatile memory array. The block PEC component can further determine which block of the superblock to write host data to next based on the quantity of PECs. The block PEC component can further write host data to the determined block.

Abstract: Methods, systems, and devices for hybrid DWLSV are described. One or more controllers may communicate one or more program commands to a NAND memory device. The memory device may perform program operations that correspond to the program commands communicated by the controller. The memory device may perform the program operations using a word line start voltage. Once the programming operations are complete, the memory device may communicate the lowest word line starting voltage offset associated with performing the program operations to the one or more controllers.

Abstract: Methods, systems, and devices for techniques for enhanced system performance after retention loss are described. A memory system may program a page of memory cells in response to receiving a power down notification. As part of the programming, the memory system may record an indication of a voltage threshold of the page and power down for a duration of time, during which the memory system may experience retention loss. Upon powering on, the memory device may compare the voltage threshold of the page to the indication stored prior to powering down and determine a voltage offset for one or more blocks of the memory system. In some cases, the memory system may use the voltage offset to determine a starting bin, and may initiate a bin scan to determine a final bin for the one or more blocks.

Abstract: Methods, systems, and devices for managing partially programmed blocks are described. Based on writing data stored in a first block to a second block, a determination of whether to program the first block into a fully programmed state may be made based on whether the first block is storing the data in the partially programmed state. Based on determining whether to program the first block, the first block may be maintained in the fully programmed state until an erase operation is performed for the first block.

Abstract: A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, a temperature of the memory block is compared to a threshold temperature range. In response to determining the temperature of the memory block is within the threshold temperature range, the processing device causes execution of a wordline leakage test of a wordline group of a set of wordline groups of the memory block. A result of the wordline leakage test of the target wordline group is determined and an action is executed based on the result of the wordline leakage test.

Abstract: Methods, systems, and devices for techniques for retiring blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. Upon determining the occurrence of the error, the memory system may identify one or more operating conditions associated with the block. For example, the memory system may determine a temperature of the block, a cycle count of the block, a quantity of times the block has experienced an error, a bit error rate of the block, and/or a quantity of available blocks in the associated system. Depending on whether a criteria associated with a respective operating condition is satisfied, the block may be enabled or retired.

Abstract: A vehicle location system may execute a model to simulate a movement of a passenger vehicle along a ride path. The vehicle location system may determine, based on executing the model, that a current ride location of the passenger vehicle is a first ride location. The vehicle location system may update a map application to indicate that the current ride location is the first ride location. The vehicle location system may receive sensor data generated by a sensor device located at a second ride location. The sensor data indicates that the passenger vehicle has been detected at the second ride location. The vehicle location system may provide the sensor data as an input to the model to update the current ride location to the second ride location. The vehicle location system may update, based on the sensor data, the map application to indicate the second ride location.

Abstract: A system includes a processor and a memory storing software code and a machine learning (ML) model. The software code is executed to receive contextual data samples each including raw data and a descriptive label, for each contextual data sample: search a database for a data pattern matching the raw data, determine, when the data pattern is detected, whether the data pattern is correlated with an anomalous event, and generate, when the correlation is determined, training data including a label identifying the anomalous event, and the raw data, the data pattern, or both, to provide one of multiple training data samples, wherein the training data samples describe anomalous events corresponding respectively to the raw data, the data pattern, or both. The software code is further executed to train the ML model, using the training data samples, to provide a trained predictive ML model configured to predict the anomalous events.

Abstract: Methods, systems, and devices for techniques for enhanced system performance after retention loss are described. A memory system may program a page of memory cells in response to receiving a power down notification. As part of the programming, the memory system may record an indication of a voltage threshold of the page and power down for a duration of time, during which the memory system may experience retention loss. Upon powering on, the memory device may compare the voltage threshold of the page to the indication stored prior to powering down and determine a voltage offset for one or more blocks of the memory system. In some cases, the memory system may use the voltage offset to determine a starting bin, and may initiate a bin scan to determine a final bin for the one or more blocks.

Abstract: A system can include a memory device with multiple management units, each management unit made up of multiple blocks, and a processing device, operatively coupled with the memory device, to perform various operations including identifying, among the management units, some complete management units and some incomplete management units, as well as performing one type of operation using one or more complete management units. The operations can also include performing another type of operation using one or more incomplete management units where this other type of operation include writing, to one or more incomplete management units, metadata associated with the data stored in complete management units.

Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a metric associated with the memory array. Responsive to determine that the value of the metric is below a predetermined threshold, the processing device is further to initiate an erase protocol of the memory device. The processing device is further to erase sets of memory cells associated with one or more memory blocks of the memory array. The processing device is further to receive a programming command directed to the first set of memory cells. The processing device is further to perform a programming operation with respect to a set of memory cells responsive to receiving the programming command.