Patents by Inventor Chun-Ta Ho

Chun-Ta Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240419208
    Abstract: A signal transmitting system comprising: a first transmitting circuit, operating according to a first operation clock signal with a first phase; a second transmitting circuit, operating according to a second operation clock signal with a second phase, wherein the first phase and the second phase are different; and a multi-phase clock signal generating circuit, coupled to the first transmitting circuit and the second transmitting circuit, to generate the first operation clock signal and the second operation clock signal.
    Type: Application
    Filed: June 13, 2024
    Publication date: December 19, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventor: Chun-Ta Ho
  • Patent number: 11581858
    Abstract: The present disclosure discloses a sample and hold amplifier circuit that includes a positive and a negative terminal capacitor arrays, a positive and a negative terminal switch arrays and a differential output circuit. A second terminal of each of bit capacitors in the positive and the negative terminal capacitor arrays are respectively coupled to a positive and a negative output terminal. In a sampling time period, according to a first connection relation, each of the connected bit capacitors is controlled to receive a polarity input voltage to perform a gain modification. In a holding time period, according to a second connection relation, each of the connected bit capacitors is controlled to receive an offset modification voltage to perform an offset modification. A positive and a negative output voltages are generated at the positive and the negative output terminal to be outputted as a pair of differential output signals by the differential output circuit.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: February 14, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Ta Ho, Shawn Min
  • Patent number: 11455000
    Abstract: The present invention discloses a bias current generation circuit. An operation amplifier compares an input voltage having a zero-temperature coefficient and a feedback voltage to generate a driving voltage. An output transistor generates a bias current according to the driving voltage. A variable resistive circuit is electrically coupled to the output transistor through a feedback node to generate the feedback voltage according to the bias current and includes series-coupled resistors and switch transistors. Each of the resistors has a resistance having a positive temperature coefficient and includes a current input terminal and a current output terminal. Each of the switch transistors is electrically coupled between the current output terminal of one of the resistors and a ground terminal. One of the switch transistors turns on according to a control voltage variable according to the temperature variation to enable resistors to generate the resistance having a negative temperature coefficient.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: September 27, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Ta Ho, Chun-I Kuo, Shawn Min
  • Patent number: 11251701
    Abstract: A high voltage tolerant output circuit includes a boost circuit, a first bias circuit, and a buffer circuit. The boost circuit includes a first transistor and an output node. A first terminal of the first transistor is coupled with the output node. The first bias circuit is coupled with the output node and a control terminal of the first transistor, and for dividing the output voltage of the output node. The first bias circuit is further configured to transmit the divided output voltage to the control terminal of the first transistor. The buffer circuit is coupled with a second terminal of the first transistor, and for setting a first voltage of the second terminal of the first transistor. The output voltage is positive correlated to the first voltage, and a maximum value of the output voltage is higher than or equal to a maximum value of the first voltage.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: February 15, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-I Kuo, Yi-Jang Wu, Chun-Ta Ho, Cheng-Yu Liu
  • Publication number: 20210263548
    Abstract: The present invention discloses a bias current generation circuit. An operation amplifier compares an input voltage having a zero-temperature coefficient and a feedback voltage to generate a driving voltage. An output transistor generates a bias current according to the driving voltage. A variable resistive circuit is electrically coupled to the output transistor through a feedback node to generate the feedback voltage according to the bias current and includes series-coupled resistors and switch transistors. Each of the resistors has a resistance having a positive temperature coefficient and includes a current input terminal and a current output terminal. Each of the switch transistors is electrically coupled between the current output terminal of one of the resistors and a ground terminal. One of the switch transistors turns on according to a control voltage variable according to the temperature variation to enable resistors to generate the resistance having a negative temperature coefficient.
    Type: Application
    Filed: February 23, 2021
    Publication date: August 26, 2021
    Inventors: CHUN-TA HO, CHUN-I KUO, SHAWN MIN
  • Publication number: 20210265957
    Abstract: The present disclosure discloses a sample and hold amplifier circuit that includes a positive and a negative terminal capacitor arrays, a positive and a negative terminal switch arrays and a differential output circuit. A second terminal of each of bit capacitors in the positive and the negative terminal capacitor arrays are respectively coupled to a positive and a negative output terminal In a sampling time period, according to a first connection relation, each of the connected bit capacitors is controlled to receive a polarity input voltage to perform a gain modification. In a holding time period, according to a second connection relation, each of the connected bit capacitors is controlled to receive an offset modification voltage to perform an offset modification. A positive and a negative output voltages are generated at the positive and the negative output terminal to be outputted as a pair of differential output signals by the differential output circuit.
    Type: Application
    Filed: February 23, 2021
    Publication date: August 26, 2021
    Inventors: CHUN-TA HO, SHAWN MIN
  • Publication number: 20210265910
    Abstract: A high voltage tolerant output circuit includes a boost circuit, a first bias circuit, and a buffer circuit. The boost circuit includes a first transistor and an output node. A first terminal of the first transistor is coupled with the output node. The first bias circuit is coupled with the output node and a control terminal of the first transistor, and for dividing the output voltage of the output node. The first bias circuit is further configured to transmit the divided output voltage to the control terminal of the first transistor. The buffer circuit is coupled with a second terminal of the first transistor, and for setting a first voltage of the second terminal of the first transistor. The output voltage is positive correlated to the first voltage, and a maximum value of the output voltage is higher than or equal to a maximum value of the first voltage.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 26, 2021
    Inventors: Chun-I Kuo, Yi-Jang Wu, Chun-Ta Ho, Cheng-Yu Liu
  • Patent number: 8179295
    Abstract: A background self-calibrated DAC is presented. A virtual-short theory, applicable to input/output terminals of an operational amplifier, is periodically employed so as to self-calibrate a current source serially connected with an equivalent resistor, and the DAC using the same. The DAC does not require an additional self-calibration period, and digital-to-analog conversion thereof can be realized in merely a small amount of die area. Correspondingly, a compact and high-speed current steering DAC can be realized.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: May 15, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chun-Ta Ho, Chuan-Ping Tu
  • Publication number: 20100289680
    Abstract: A background self-calibrated DAC is presented. In the present invention, a virtual-short theory, applicable to input/output terminals of an operational amplifier, is periodically employed so as to self-calibrate a current source serially connected with an equivalent resistor, and the DAC using the same. The aforesaid DAC does not require an additional self-calibration period, and digital-to-analog conversion thereof can be realized in merely a small amount of die area. Correspondingly, a compact and high-speed current steering DAC can be realized.
    Type: Application
    Filed: May 13, 2010
    Publication date: November 18, 2010
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chun-Ta Ho, Chuan-Ping Tu
  • Patent number: 7308724
    Abstract: A household bathing water massage device comprised of a shower head connected below an existent cold and hot water faucet with a water volume controller installed in between, a three-way connector installed at the lower end, and a hose respectively connected to the controller and filter. The controller has an internally disposed pressurizing motor, frequency transformer, microcontroller board, and remote control unit, with the remote control unit equipped with a plurality of push-type keys. Furthermore, the end of the hose provides for the installation of water discharge nozzles. As such, user operation varies the intensity of the water output force as well as changes in water volume duration, utilizing the shower head accessories and differently shaped nozzles to produce streams of differing force directed against the body for water massage applications, thereby revitalizing cells, eliminating fatigue, and promoting metabolism to comfortably relax the body and spirit.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: December 18, 2007
    Inventor: Chun-Ta Ho
  • Publication number: 20060218721
    Abstract: A household bathing water massage device comprised of a shower head connected below an existent cold and hot water faucet with a water volume controller installed in between, a three-way connector installed at the lower end, and a hose respectively connected to the controller and filter. The controller has an internally disposed pressurizing motor, frequency transformer, microcontroller board, and remote control unit, with the remote control unit equipped with a plurality of push-type keys. Furthermore, the end of the hose provides for the installation of water discharge nozzles. As such, user operation varies the intensity of the water output force as well as changes in water volume duration, utilizing the shower head accessories and differently shaped nozzles to produce streams of differing force directed against the body for water massage applications, thereby revitalizing cells, eliminating fatigue, and promoting metabolism to comfortably relax the body and spirit.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 5, 2006
    Inventor: Chun-Ta Ho