Abstract: An apparatus, program product and method provide on-demand numerical conversion of convertible numerical values such as measurements and monetary values. A numerical value that is displayed in a document such as a web page, and that is represented in a native unit, may be converted to a value represented in a local unit for a user viewing the document. That converted numerical value may then be displayed adjacent the original numerical value, and typically along with an indication of the local unit, in response to the user positioning a pointer over the original (unconverted) numerical value, so that the user can quickly comprehend the numerical value in units to which he or she is accustomed.

Abstract: A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test row includes the access detection circuit, which provides the same loading during an access operation as the other cells in the array. The access detection circuit provides an output that may be probed without affecting the timing, read stability or writeability of the cell. The test row can test the clock and/or address timing of the row and may include a separate power supply rail for the row wordline driver, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.

Abstract: Disclosed is a metal fill region of a semiconductor chip including a plurality of layer sets of the semiconductor chip, each set including a first metal fill layer, a second metal fill layer, and an insulation layer included disposed in planes parallel to each other, a plurality of metal fill pieces disposed in each of the metal fill layers, a metal fill piece axis of each of the pieces, wherein each of the axes perpendicularly intersects the planes of said metal fill layers and the insulation layer from any point of reference, and a metal fill pattern configured to position the pieces so that the axis of each piece in the first metal fill layer is linearly displaced of the axis of each piece in the second metal fill layer in at least one direction orthogonal to each of the metal fill axes.

Abstract: A method and an apparatus are disclosed for the display of hierarchical navigation in the automated design of integrated circuits under test. A user, using a computer, assigns a head pointer assignment and a tail pointer assignment, which form a definition of a viewable scope of at least one hierarchical level of design from a plurality of hierarchical levels of design. These head pointer and tail pointer assignments are stored in a repository of the computer to set the definition of the viewable scope of the at least one hierarchical level of design. After being set, the viewable scope of the at least one hierarchical level of design is displayed on a computer display device, where the viewable scope of the at least one hierarchical level of design can be traversed by moving a scrolling mechanism up and down in the viewable scope of the at least one hierarchical level of design.

Abstract: A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test row includes the access detection circuit, which provides the same loading during an access operation as the other cells in the array. The access detection circuit provides an output that may be probed without affecting the timing, read stability or writeability of the cell. The test row can test the clock and/or address timing of the row and may include a separate power supply rail for the row wordline driver, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.

Abstract: Z-axis display navigation in the design automation process of physical design, development and manufacturing of integrated circuits includes pre-selecting, using a computer mouse connected to a computer workstation processor, viewable graphical layout layers desired by a design layout debugging operator to view during an integrated circuit (IC) design debugging process. After selecting the desired viewable graphic layout layers, the layout operator uses the mouse to traverse the pre-selected viewable graphical layout layers displayed, by changing the input scrolling pattern of the mouse to scroll forward, backward, diagonally and from side to side in a plurality of directions, where a curser on the layout screen will correspondingly move in the plurality of directions in the pre-selected viewable graphical layout layers on the layout screen corresponding to the movement of the mouse by the operator.

Abstract: A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.

Abstract: A method and apparatus implement improved timing performance of a signal bus through wire permutation with repowering buffers. A repowering buffer includes a prebuffer and a postbuffer. A plurality of prebuffers and postbuffers are stored in a design library, each having a set wiring ordered arrangement for selectively providing wire permutation of the signal bus. A wiring order of prebuffer at the beginning of the bus is identical to the wiring order of the postbuffer at the end of bus. The wiring order of the postbuffer driving the beginning of bus wires between adjacent repowering buffers is identical to the wiring order of the prebuffer receiving at the end of the bus wires. A wiring order of the downstream buffer pairs is chosen so that there is at least one pair of wires separated by another wire or wires in the bus.

Abstract: A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.

Abstract: Disclosed is a metal fill region of a semiconductor chip including a plurality of layer sets of the semiconductor chip, each set including a first metal fill layer, a second metal fill layer, and an insulation layer included disposed in planes parallel to each other, a plurality of metal fill pieces disposed in each of the metal fill layers, a metal fill piece axis of each of the pieces, wherein each of the axes perpendicularly intersects the planes of said metal fill layers and the insulation layer from any point of reference, and a metal fill pattern configured to position the pieces so that the axis of each piece in the first metal fill layer is linearly displaced of the axis of each piece in the second metal fill layer in at least one direction orthogonal to each of the metal fill axes.

Abstract: A design structure embodied in a machine readable medium used in a design process includes a metal fill region of a semiconductor chip including a plurality of layer sets of the semiconductor chip, each set including a first metal fill layer, a second metal fill layer, and an insulation layer included disposed in planes parallel to each other, a plurality of metal fill pieces disposed in each of the metal fill layers, a metal fill piece axis of each of the pieces, wherein each of the axes perpendicularly intersects the planes of said metal fill layers and the insulation layer from any point of reference, and a metal fill pattern configured to position the pieces so that the axis of each piece in the first metal fill layer is linearly displaced of the axis of each piece in the second metal fill layer in at least one direction orthogonal to each of the metal fill axes.

Abstract: An apparatus, program product and method provide on-demand numerical conversion of convertible numerical values such as measurements and monetary values. A numerical value that is displayed in a document such as a web page, and that is represented in a native unit, may be converted to a value represented in a local unit for a user viewing the document. That converted numerical value may then be displayed adjacent the original numerical value, and typically along with an indication of the local unit, in response to the user positioning a pointer over the original (unconverted) numerical value, so that the user can quickly comprehend the numerical value in units to which he or she is accustomed.