Patents by Inventor Chun Te Lin
Chun Te Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240142428Abstract: A water quality detection device including a detection tank, a sensor, the cleaner and a processor is provided. The sensor is disposed on the detection tank and is configured to sense a to-be-detected liquid within the detection tank. The cleaner is configured to clean the sensor. The processor is electrically connected to the sensor and the cleaner and is configured to: execute an initialization procedure, which includes driving the sensor to sense the to-be-detected liquid to obtain a number of initial sensing values and calculating a threshold value according to the initial sensing values; drive the sensor to sense the to-be-detected liquid to obtain a sensing value of the to-be-detected liquid, and determine whether the sensing value of the to-be-detected liquid reaches the threshold value; drive the cleaner to operate when the sensing value of the to-be-detected liquid reaches the threshold value.Type: ApplicationFiled: February 17, 2023Publication date: May 2, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tsung-Yu TSAI, Hung-Sheng LIN, Cheng-Da KO, Chun-Te CHUANG
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Patent number: 11942367Abstract: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.Type: GrantFiled: December 7, 2020Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chan Syun David Yang, Li-Te Lin, Chun-Jui Huang
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Patent number: 11937932Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.Type: GrantFiled: July 8, 2022Date of Patent: March 26, 2024Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITYInventors: Chieh-Liang Wu, Chun-Te Huang, Cheng-Hsu Chen, Tsai-Jung Wang, Kai-Chih Pai, Chun-Ming Lai, Min-Shian Wang, Ruey-Kai Sheu, Lun-Chi Chen, Yan-Nan Lin, Chien-Lun Liao, Ta-Chun Hung, Chien-Chung Huang, Chia-Tien Hsu, Shang-Feng Tsai
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Patent number: 11935894Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.Type: GrantFiled: November 4, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
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Patent number: 11916314Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.Type: GrantFiled: May 12, 2022Date of Patent: February 27, 2024Assignee: HTC CorporationInventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
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Patent number: 11694950Abstract: A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.Type: GrantFiled: March 11, 2021Date of Patent: July 4, 2023Assignee: Powertech Technology Inc.Inventors: Chih-Yen Su, Chun-Te Lin
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Patent number: 11362055Abstract: The semiconductor package has a metal layer, a first dielectric layer formed on a metal layer, and an opening formed through the first dielectric layer to expose a part of the metal layer. The bump structure has an under bump metallurgy (hereinafter UBM), a first buffer layer and a metal bump. The UBM is formed on the first part of the metal layer, a sidewall of the opening and a top surface of the first dielectric layer. The first buffer layer is formed between a part of the UBM corresponding to the top surface of the first dielectric layer and the top surface of the first dielectric layer. The metal bump is formed on the UBM. Therefore, the first buffer layer effectively absorbs a thermal stress to avoid cracks generated in the bump structure after the bonding step.Type: GrantFiled: November 12, 2020Date of Patent: June 14, 2022Assignee: Powertech Technology Inc.Inventors: Chih-Yen Su, Chun-Te Lin
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Publication number: 20220148955Abstract: A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.Type: ApplicationFiled: March 11, 2021Publication date: May 12, 2022Applicant: Powertech Technology Inc.Inventors: Chih-Yen SU, Chun-Te Lin
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Patent number: 11302539Abstract: A method for packaging a semiconductor device includes the steps of: disposing a wafer on a first carrier plate; attaching a second carrier plate to a side of the first carrier plate opposite to the wafer; disposing a chip unit on a side of the wafer opposite to the first carrier plate; and covering the wafer and the chip unit with an encapsulation layer. A semiconductor packaging structure is also disclosed.Type: GrantFiled: August 7, 2020Date of Patent: April 12, 2022Assignee: Powertech Technology Inc.Inventors: Tsung-Han Chiang, Chun-Te Lin
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Publication number: 20220037274Abstract: The semiconductor package has a metal layer, a first dielectric layer formed on a metal layer, and an opening formed through the first dielectric layer to expose a part of the metal layer. The bump structure has an under bump metallurgy (hereinafter UBM), a first buffer layer and a metal bump. The UBM is formed on the first part of the metal layer, a sidewall of the opening and a top surface of the first dielectric layer. The first buffer layer is formed between a part of the UBM corresponding to the top surface of the first dielectric layer and the top surface of the first dielectric layer. The metal bump is formed on the UBM. Therefore, the first buffer layer effectively absorbs a thermal stress to avoid cracks generated in the bump structure after the bonding step.Type: ApplicationFiled: November 12, 2020Publication date: February 3, 2022Applicant: Powertech Technology Inc.Inventors: Chih-Yen SU, Chun-Te LIN
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Publication number: 20210351044Abstract: A method for packaging a semiconductor device includes the steps of: disposing a wafer on a first carrier plate; attaching a second carrier plate to a side of the first carrier plate opposite to the wafer; disposing a chip unit on a side of the wafer opposite to the first carrier plate; and covering the wafer and the chip unit with an encapsulation layer. A semiconductor packaging structure is also disclosed.Type: ApplicationFiled: August 7, 2020Publication date: November 11, 2021Applicant: Powertech Technology Inc.Inventors: Tsung-Han CHIANG, Chun-Te LIN
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Patent number: 11133291Abstract: A chip package structure including a circuit board, a first die, a spacer, and a second die. The first die is disposed on the circuit board, and the spacer is disposed on the circuit board, in which the spacer includes a spacer part and at least one via structure penetrating through the spacer part. The second die is disposed on the first die and the spacer, and the second die is electrically connected to the circuit board through the spacer.Type: GrantFiled: March 13, 2020Date of Patent: September 28, 2021Assignee: POWERTECH TECHNOLOGY INC.Inventors: Chih-Yen Su, Chun-Te Lin
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Publication number: 20210202444Abstract: A chip package structure including a circuit board, a first die, a spacer, and a second die. The first die is disposed on the circuit board, and the spacer is disposed on the circuit board, in which the spacer includes a spacer part and at least one via structure penetrating through the spacer part. The second die is disposed on the first die and the spacer, and the second die is electrically connected to the circuit board through the spacer.Type: ApplicationFiled: March 13, 2020Publication date: July 1, 2021Inventors: Chih-Yen Su, Chun-Te Lin
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Patent number: 10950557Abstract: A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.Type: GrantFiled: February 4, 2020Date of Patent: March 16, 2021Assignee: Powertech Technology Inc.Inventors: Li-Chih Fang, Ji-Cheng Lin, Che-Min Chu, Chun-Te Lin, Chien-Wen Huang
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Patent number: D935399Type: GrantFiled: March 31, 2020Date of Patent: November 9, 2021Assignee: Acer IncorporatedInventors: Chun-Te Lin, Tsun-Chih Yang
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Patent number: D939024Type: GrantFiled: January 14, 2020Date of Patent: December 21, 2021Assignee: Acer IncorporatedInventors: Chun-Te Lin, Tsun-Chih Yang
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Patent number: D955383Type: GrantFiled: April 10, 2020Date of Patent: June 21, 2022Assignee: Acer IncorporatedInventors: Chun-Te Lin, Tsun-Chih Yang
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Patent number: D998278Type: GrantFiled: March 31, 2020Date of Patent: September 5, 2023Assignee: Acer IncorporatedInventors: Chun-Te Lin, Tsun-Chih Yang
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Patent number: D1022973Type: GrantFiled: November 17, 2022Date of Patent: April 16, 2024Assignee: Acer IncorporatedInventors: Chun-Te Lin, Tsun-Chih Yang
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Patent number: D1024021Type: GrantFiled: October 21, 2022Date of Patent: April 23, 2024Assignee: Acer IncorporatedInventors: Chun-Te Lin, Tsun-Chih Yang