Patents by Inventor Chun-Ting Liao
Chun-Ting Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153154Abstract: A coordinate generation system, a coordinate generation method, a computer readable recording medium with stored program, and a non-transitory computer program product are provided. The coordinate generation system includes processing units and a neural network module. The processing units are configured to obtain four vertex coordinates of an image. The vertex coordinates include first components and second components. The processing unit is configured to perform the following steps: obtaining first vector based on the first components of the four vertex coordinates and repeatedly concatenating the first vector so as to obtain a first input; obtaining second vector based on the second components of the four vertex coordinates and repeatedly concatenating the second vector so as to obtain a second input; and obtaining first output coordinate components and second output coordinate components of output coordinates based on the first input, the second input, and parameters of the neural network module.Type: ApplicationFiled: January 17, 2023Publication date: May 9, 2024Applicant: REALTEK SEMICONDUCTOR CORP.Inventors: Yu-Hsuan Hung, Chun-Fu Liao, Kai-Ting Shr
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Publication number: 20240145867Abstract: A separator for a lithium battery and a method for manufacturing the same are provided. The separator includes a substrate layer and a coating layer. The substrate layer is a polyolefin porous film and has a substrate thickness ranging from 10 to 30 micrometers. The coating layer is coated on the substrate layer, and has a coating layer thickness ranging from 1 to 5 micrometers. The coating layer includes a heat-resistant resin material and a plurality of inorganic ceramic particles glued in the heat-resistant resin material. The heat-resistant resin material has a melting point (Tm) or a glass transition temperature (Tg) of not less than 150° C. An average particle size of the inorganic ceramic particles is 10% to 40% of the coating layer thickness of the coating layer. The inorganic ceramic particles are stacked in the coating layer with a height of at least three layers.Type: ApplicationFiled: January 17, 2023Publication date: May 2, 2024Inventors: TE-CHAO LIAO, CHUN-CHE TSAO, CHENG-HUNG CHEN, LI-TING WANG
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Publication number: 20240141922Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.Type: ApplicationFiled: January 9, 2024Publication date: May 2, 2024Applicant: Acer IncorporatedInventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
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Patent number: 11946483Abstract: A fan is provided herein, including a housing, a hub, and a plurality of blades. The housing includes a top case and a bottom case. The hub is rotatably disposed between the top case and the bottom case in an axial direction. The blades extend from the hub in a radial direction, located between the top case and the bottom case. Each of the blades has a proximal end and a distal end. The proximal end is connected to the hub. The distal end is opposite from the proximal end, located at the other side of the blade, having at least one recessed portion. Each of the recessed portions form a passage for air.Type: GrantFiled: May 17, 2023Date of Patent: April 2, 2024Assignee: ACER INCORPORATEDInventors: Jau-Han Ke, Tsung-Ting Chen, Chun-Chieh Wang, Yu-Ming Lin, Cheng-Wen Hsieh, Wen-Neng Liao
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Patent number: 11913472Abstract: A centrifugal heat dissipation fan including a housing and an impeller disposed in the housing on an axis is provided. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions. A heat dissipation system of an electronic device is also provided.Type: GrantFiled: April 6, 2021Date of Patent: February 27, 2024Assignee: Acer IncorporatedInventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
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Patent number: 11791285Abstract: A device includes an outer seal ring, an integrated circuit, and an inner seal ring. The outer seal ring forms a first closed loop. The integrated circuit is surrounded by the outer seal ring. The inner seal ring is between the outer seal ring and the integrated circuit. The inner seal ring forms a second closed loop that defines an enclosed region external to the integrated circuit.Type: GrantFiled: May 13, 2021Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Hui Yang, Chun-Ting Liao, Yi-Te Chen, Chen-Yuan Chen, Ho-Chun Liou
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Publication number: 20230238337Abstract: A device includes an integrated circuit, a first seal ring, a second seal ring, and a dielectric layer. The first seal ring surrounds the integrated circuit and includes a plurality of first seal portions separated from each other by a plurality of first gaps. The second seal ring surrounds the integrated circuit, between the integrated circuit and the first seal ring and includes a plurality of second seal portions separated from each other by a plurality of second gaps. The dielectric layer surrounds the first and second seal rings and includes a plurality of first filling portions in the first gaps, respectively, and a plurality of second filling portions in the second gaps, respectively. A connection line of one of the first filling portions and one of the second filling portions closest to said one of the first filling portions is not parallel to edges of the integrated circuit.Type: ApplicationFiled: March 28, 2023Publication date: July 27, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Hui YANG, Chun-Ting LIAO, Yi-Te CHEN, Chen-Yuan CHEN, Ho-Chun LIOU
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Publication number: 20210265285Abstract: A device includes an outer seal ring, an integrated circuit, and an inner seal ring. The outer seal ring forms a first closed loop. The integrated circuit is surrounded by the outer seal ring. The inner seal ring is between the outer seal ring and the integrated circuit. The inner seal ring forms a second closed loop that defines an enclosed region external to the integrated circuit.Type: ApplicationFiled: May 13, 2021Publication date: August 26, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Hui YANG, Chun-Ting LIAO, Yi-Te CHEN, Chen-Yuan CHEN, Ho-Chun LIOU
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Patent number: 11011478Abstract: A semiconductor device includes an integrated circuit, an outer seal ring, and an inner seal ring. The outer seal ring forms a first closed loop surrounding the integrated circuit. The inner seal ring is between the outer seal ring and the integrated circuit. The inner seal ring has a first seal portion surrounding the integrated circuit and a second seal portion spaced apart from the first seal portion, a first connector interconnecting the first seal portion and the second seal portion, and a second connector spaced apart from the first connector and interconnecting the first seal portion and the second seal portion. The first seal portion, the second seal portion, the first connector, and the second connector form a second closed loop.Type: GrantFiled: July 26, 2019Date of Patent: May 18, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Hui Yang, Chun-Ting Liao, Yi-Te Chen, Chen-Yuan Chen, Ho-Chun Liou
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Patent number: 10930599Abstract: A method of manufacturing a semiconductor device comprises forming an integrated circuit, surrounding the integrated circuit with an inner seal ring, and surrounding the inner seal ring with a closed-loop outer seal ring. The inner seal ring includes a plurality of metal layers in a stacked configuration, first and second seal portions separated from each other, and third and fourth seal portions spaced apart from the first and second seal portions and separated from each other.Type: GrantFiled: November 30, 2018Date of Patent: February 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Hui Yang, Chun-Ting Liao, Yi-Te Chen, Chen-Yuan Chen, Ho-Chun Liou
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Patent number: 10714384Abstract: A semiconductor device includes an integrated circuit and a guard ring. The integrated circuit includes a first circuit and a second circuit separated from the first circuit. The guard ring is disposed around the first circuit and between the first circuit and the second circuit. The guard ring includes an outer ring, an inner ring, and two connectors. The outer ring is disposed around the first circuit and has a first gap. The inner ring is disposed between the outer ring and the first circuit and has a second gap. The two connectors connect the outer ring and the inner ring. The outer ring, the inner ring, and the two connectors form a closed loop.Type: GrantFiled: August 5, 2019Date of Patent: July 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Ming-Hui Yang, Chun-Ting Liao, Chen-Yuan Chen, Ho-Chun Liou, Yi-Te Chen
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Publication number: 20190363007Abstract: A semiconductor device includes an integrated circuit and a guard ring. The integrated circuit includes a first circuit and a second circuit separated from the first circuit. The guard ring is disposed around the first circuit and between the first circuit and the second circuit. The guard ring includes an outer ring, an inner ring, and two connectors. The outer ring is disposed around the first circuit and has a first gap. The inner ring is disposed between the outer ring and the first circuit and has a second gap. The two connectors connect the outer ring and the inner ring. The outer ring, the inner ring, and the two connectors form a closed loop.Type: ApplicationFiled: August 5, 2019Publication date: November 28, 2019Inventors: Ming-Hui YANG, Chun-Ting LIAO, Chen-Yuan CHEN, Ho-Chun LIOU, Yi-Te CHEN
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Publication number: 20190348376Abstract: A semiconductor device includes an integrated circuit, an outer seal ring, and an inner seal ring. The outer seal ring forms a first closed loop surrounding the integrated circuit. The inner seal ring is between the outer seal ring and the integrated circuit. The inner seal ring has a first seal portion surrounding the integrated circuit and a second seal portion spaced apart from the first seal portion, a first connector interconnecting the first seal portion and the second seal portion, and a second connector spaced apart from the first connector and interconnecting the first seal portion and the second seal portion. The first seal portion, the second seal portion, the first connector, and the second connector form a second closed loop.Type: ApplicationFiled: July 26, 2019Publication date: November 14, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Hui YANG, Chun-Ting LIAO, Yi-Te CHEN, Chen-Yuan CHEN, Ho-Chun LIOU
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Patent number: 10373865Abstract: A semiconductor device includes an integrated circuit and a guard ring. The integrated circuit includes a first circuit and a second circuit separated from the first circuit. The guard ring is disposed around the first circuit and between the first circuit and the second circuit. The guard ring includes an outer ring, an inner ring, and two connectors. The outer ring is disposed around the first circuit and has a first gap. The inner ring is disposed between the outer ring and the first circuit and has a second gap. The two connectors connect the outer ring and the inner ring. The outer ring, the inner ring, and the two connectors form a closed loop.Type: GrantFiled: July 24, 2015Date of Patent: August 6, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Ming-Hui Yang, Chun-Ting Liao, Chen-Yuan Chen, Ho-Chun Liou, Yi-Te Chen
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Patent number: 10366956Abstract: A semiconductor device includes an integrated circuit, at least one outer seal ring, and at least one inner seal ring. The outer seal ring surrounds the integrated circuit. The outer seal ring includes a plurality of metal layers in a stacked configuration, and the metal layers are closed loops. The inner seal ring is disposed between the outer seal ring and the integrated circuit and separated from the outer seal ring. The inner seal ring has at least one gap extending from a region encircled by the inner seal ring to a region outside the inner seal ring.Type: GrantFiled: July 9, 2015Date of Patent: July 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Hui Yang, Chun-Ting Liao, Yi-Te Chen, Chen-Yuan Chen, Ho-Chun Liou
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Publication number: 20190096827Abstract: A method of manufacturing a semiconductor device comprises forming an integrated circuit, surrounding the integrated circuit with an inner seal ring, and surrounding the inner seal ring with a closed-loop outer seal ring. The inner seal ring includes a plurality of metal layers in a stacked configuration, first and second seal portions separated from each other, and third and fourth seal portions spaced apart from the first and second seal portions and separated from each other.Type: ApplicationFiled: November 30, 2018Publication date: March 28, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Hui YANG, Chun-Ting LIAO, Yi-Te CHEN, Chen-Yuan CHEN, Ho-Chun LIOU
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Publication number: 20170025367Abstract: A semiconductor device includes an integrated circuit and a guard ring. The integrated circuit includes a first circuit and a second circuit separated from the first circuit. The guard ring is disposed around the first circuit and between the first circuit and the second circuit. The guard ring includes an outer ring, an inner ring, and two connectors. The outer ring is disposed around the first circuit and has a first gap. The inner ring is disposed between the outer ring and the first circuit and has a second gap. The two connectors connect the outer ring and the inner ring. The outer ring, the inner ring, and the two connectors form a closed loop.Type: ApplicationFiled: July 24, 2015Publication date: January 26, 2017Inventors: Ming-Hui YANG, Chun-Ting LIAO, Chen-Yuan CHEN, Ho-Chun LIOU, Yi-Te CHEN
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Publication number: 20160365318Abstract: A semiconductor device includes an integrated circuit, at least one outer seal ring, and at least one inner seal ring. The outer seal ring surrounds the integrated circuit. The outer seal ring includes a plurality of metal layers in a stacked configuration, and the metal layers are closed loops. The inner seal ring is disposed between the outer seal ring and the integrated circuit and separated from the outer seal ring. The inner seal ring has at least one gap extending from a region encircled by the inner seal ring to a region outside the inner seal ring.Type: ApplicationFiled: July 9, 2015Publication date: December 15, 2016Inventors: Ming-Hui YANG, Chun-Ting LIAO, Yi-Te CHEN, Chen-Yuan CHEN, Ho-Chun LIOU
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Patent number: 9088291Abstract: The present invention disclosed a Universal Serial Bus (USB) apparatus. The apparatus includes: a signal detecting unit for detecting a packet signal transmitted from a USB host and generating an acknowledgment signal according to a detection result; an error detecting unit, coupled to the signal detecting unit, for generating a control signal according to the acknowledgment signal; and a frequency generating unit, coupled to the error detecting unit, for generating an output clock signal according to the control signal.Type: GrantFiled: October 23, 2006Date of Patent: July 21, 2015Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Chun-Ting Liao, An-Ming Lee, Jun-Jie Xie, Ying-Hui Zhu
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Patent number: 8377787Abstract: A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the semiconductor substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.Type: GrantFiled: June 8, 2011Date of Patent: February 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Liang Chu, Chun-Ting Liao, Fei-Yuh Chen, Tsung-Yi Huang