Abstract: A device includes an outer seal ring, an integrated circuit, and an inner seal ring. The outer seal ring forms a first closed loop. The integrated circuit is surrounded by the outer seal ring. The inner seal ring is between the outer seal ring and the integrated circuit. The inner seal ring forms a second closed loop that defines an enclosed region external to the integrated circuit.

Abstract: A device includes an integrated circuit, a first seal ring, a second seal ring, and a dielectric layer. The first seal ring surrounds the integrated circuit and includes a plurality of first seal portions separated from each other by a plurality of first gaps. The second seal ring surrounds the integrated circuit, between the integrated circuit and the first seal ring and includes a plurality of second seal portions separated from each other by a plurality of second gaps. The dielectric layer surrounds the first and second seal rings and includes a plurality of first filling portions in the first gaps, respectively, and a plurality of second filling portions in the second gaps, respectively. A connection line of one of the first filling portions and one of the second filling portions closest to said one of the first filling portions is not parallel to edges of the integrated circuit.

Abstract: A device includes an outer seal ring, an integrated circuit, and an inner seal ring. The outer seal ring forms a first closed loop. The integrated circuit is surrounded by the outer seal ring. The inner seal ring is between the outer seal ring and the integrated circuit. The inner seal ring forms a second closed loop that defines an enclosed region external to the integrated circuit.

Abstract: A semiconductor device includes an integrated circuit, an outer seal ring, and an inner seal ring. The outer seal ring forms a first closed loop surrounding the integrated circuit. The inner seal ring is between the outer seal ring and the integrated circuit. The inner seal ring has a first seal portion surrounding the integrated circuit and a second seal portion spaced apart from the first seal portion, a first connector interconnecting the first seal portion and the second seal portion, and a second connector spaced apart from the first connector and interconnecting the first seal portion and the second seal portion. The first seal portion, the second seal portion, the first connector, and the second connector form a second closed loop.

Abstract: A method of manufacturing a semiconductor device comprises forming an integrated circuit, surrounding the integrated circuit with an inner seal ring, and surrounding the inner seal ring with a closed-loop outer seal ring. The inner seal ring includes a plurality of metal layers in a stacked configuration, first and second seal portions separated from each other, and third and fourth seal portions spaced apart from the first and second seal portions and separated from each other.

Abstract: A semiconductor device includes an integrated circuit and a guard ring. The integrated circuit includes a first circuit and a second circuit separated from the first circuit. The guard ring is disposed around the first circuit and between the first circuit and the second circuit. The guard ring includes an outer ring, an inner ring, and two connectors. The outer ring is disposed around the first circuit and has a first gap. The inner ring is disposed between the outer ring and the first circuit and has a second gap. The two connectors connect the outer ring and the inner ring. The outer ring, the inner ring, and the two connectors form a closed loop.

Abstract: A semiconductor device includes an integrated circuit and a guard ring. The integrated circuit includes a first circuit and a second circuit separated from the first circuit. The guard ring is disposed around the first circuit and between the first circuit and the second circuit. The guard ring includes an outer ring, an inner ring, and two connectors. The outer ring is disposed around the first circuit and has a first gap. The inner ring is disposed between the outer ring and the first circuit and has a second gap. The two connectors connect the outer ring and the inner ring. The outer ring, the inner ring, and the two connectors form a closed loop.

Abstract: A semiconductor device includes an integrated circuit, an outer seal ring, and an inner seal ring. The outer seal ring forms a first closed loop surrounding the integrated circuit. The inner seal ring is between the outer seal ring and the integrated circuit. The inner seal ring has a first seal portion surrounding the integrated circuit and a second seal portion spaced apart from the first seal portion, a first connector interconnecting the first seal portion and the second seal portion, and a second connector spaced apart from the first connector and interconnecting the first seal portion and the second seal portion. The first seal portion, the second seal portion, the first connector, and the second connector form a second closed loop.

Abstract: A semiconductor device includes an integrated circuit and a guard ring. The integrated circuit includes a first circuit and a second circuit separated from the first circuit. The guard ring is disposed around the first circuit and between the first circuit and the second circuit. The guard ring includes an outer ring, an inner ring, and two connectors. The outer ring is disposed around the first circuit and has a first gap. The inner ring is disposed between the outer ring and the first circuit and has a second gap. The two connectors connect the outer ring and the inner ring. The outer ring, the inner ring, and the two connectors form a closed loop.

Abstract: A semiconductor device includes an integrated circuit, at least one outer seal ring, and at least one inner seal ring. The outer seal ring surrounds the integrated circuit. The outer seal ring includes a plurality of metal layers in a stacked configuration, and the metal layers are closed loops. The inner seal ring is disposed between the outer seal ring and the integrated circuit and separated from the outer seal ring. The inner seal ring has at least one gap extending from a region encircled by the inner seal ring to a region outside the inner seal ring.

Abstract: A method of manufacturing a semiconductor device comprises forming an integrated circuit, surrounding the integrated circuit with an inner seal ring, and surrounding the inner seal ring with a closed-loop outer seal ring. The inner seal ring includes a plurality of metal layers in a stacked configuration, first and second seal portions separated from each other, and third and fourth seal portions spaced apart from the first and second seal portions and separated from each other.

Abstract: A semiconductor device includes an integrated circuit and a guard ring. The integrated circuit includes a first circuit and a second circuit separated from the first circuit. The guard ring is disposed around the first circuit and between the first circuit and the second circuit. The guard ring includes an outer ring, an inner ring, and two connectors. The outer ring is disposed around the first circuit and has a first gap. The inner ring is disposed between the outer ring and the first circuit and has a second gap. The two connectors connect the outer ring and the inner ring. The outer ring, the inner ring, and the two connectors form a closed loop.

Abstract: A semiconductor device includes an integrated circuit, at least one outer seal ring, and at least one inner seal ring. The outer seal ring surrounds the integrated circuit. The outer seal ring includes a plurality of metal layers in a stacked configuration, and the metal layers are closed loops. The inner seal ring is disposed between the outer seal ring and the integrated circuit and separated from the outer seal ring. The inner seal ring has at least one gap extending from a region encircled by the inner seal ring to a region outside the inner seal ring.

Abstract: The present invention disclosed a Universal Serial Bus (USB) apparatus. The apparatus includes: a signal detecting unit for detecting a packet signal transmitted from a USB host and generating an acknowledgment signal according to a detection result; an error detecting unit, coupled to the signal detecting unit, for generating a control signal according to the acknowledgment signal; and a frequency generating unit, coupled to the error detecting unit, for generating an output clock signal according to the control signal.

Abstract: A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the semiconductor substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.

Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.

Abstract: An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.

Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.

Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.

Abstract: A data writing method for flash memory and an error correction encoding/decoding method thereof are disclosed. In an embodiment of the data writing method, a 6-bit ECC scheme using a Reed-Solomon code derived from a Galois Field GF (29) is used to encode a data for generating a redundant which requires smaller storing space. In an embodiment of the error correction encoding/decoding method, an erase checking value corresponding to the status where all the bytes of data area and parameter storing area are “0xff” is provided to improve the security of stored data.