Patents by Inventor Chun-Ting Lu

Chun-Ting Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250079765
    Abstract: A memory socket includes a frame having a base portion and a side portion, and a push-eject locking mechanism in physical communication with the base portion and with the side portion. The push-eject locking mechanism to transition between an unlocked position and a locked position. The push-eject locking mechanism includes an eject bar component and a lever component. The weight of the eject bar component biases the push-eject locking mechanism towards the unlocked position. Based on a force being exerted on the lever component, the lever component pivots and transition the push-eject locking mechanism from the unlocked position to the locked position.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 6, 2025
    Inventors: Chun-Ting Lu, JerYo Lee, Cheng-Hsiang Chuang, Yo-Huang Chang
  • Patent number: 12170176
    Abstract: A multiple function button for an information handling system includes an outer button and an inner button. The outer button includes a first contact component positioned over a first contact of the information handling system. The first contact is associated with a first operation within the information handling system. The inner button is inserted within the outer button and includes a second contact component. The second contact component is positioned over a second contact of the information handling system, which in turn is associated with a second operation within the information handling system.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: December 17, 2024
    Assignee: Dell Products L.P.
    Inventors: Jer-Yo Lee, Chun-Ting Lu, Cheng-Hsiang Chuang
  • Patent number: 12099663
    Abstract: An information handling system includes a keyboard with multiple customizable click feeling keys. A first customizable click feeling key includes a keycap magnet and an electromagnet. The keycap magnet includes a first magnetic polarity portion and a second magnetic polarity portion. The system communicates individually with each of the customizable click feeling keys to determine a mode. Based on the mode being a first mode, the system provides a first current to the electromagnet to generate a first magnetic pole strength within the electromagnet. Based on the mode being a second mode, the system provides a second current to the electromagnet to generate a second magnetic pole strength within the electromagnet. The second magnetic pole strength creates a stronger repulsion force between the electromagnet and the keycap magnet.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: September 24, 2024
    Assignee: Dell Products L.P.
    Inventors: JerYo Lee, Cheng-Hsiang Chuang, Chun-Ting Lu
  • Publication number: 20240272727
    Abstract: An information handling system includes a keyboard with multiple customizable click feeling keys. A first customizable click feeling key includes a keycap magnet and an electromagnet. The keycap magnet includes a first magnetic polarity portion and a second magnetic polarity portion. The system communicates individually with each of the customizable click feeling keys to determine a mode. Based on the mode being a first mode, the system provides a first current to the electromagnet to generate a first magnetic pole strength within the electromagnet. Based on the mode being a second mode, the system provides a second current to the electromagnet to generate a second magnetic pole strength within the electromagnet. The second magnetic pole strength creates a stronger repulsion force between the electromagnet and the keycap magnet.
    Type: Application
    Filed: February 10, 2023
    Publication date: August 15, 2024
    Inventors: JerYo Lee, Cheng-Hsiang Chuang, Chun-Ting Lu
  • Patent number: 11990291
    Abstract: A multiple function button for an information handling system includes an outer shell and an inner button. The outer shell includes multiple channels having first, second, third and fourth channels. The inner button is inserted within the outer shell. The inner button includes a tab and a contact component. The tab moves within the multiple channels. When the tab is within the first channel, the inner button is in a first position and contact component is positioned over a first contact of the information handling system. When the tab is within the third channel, the inner button is in a second position and the contact component is positioned over a second contact of the information handling system.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: May 21, 2024
    Assignee: Dell Products L.P.
    Inventors: Jer-Yo Lee, Chun-Ting Lu, Cheng-Hsiang Chuang
  • Publication number: 20230386764
    Abstract: A multiple function button for an information handling system includes an outer shell and an inner button. The outer shell includes multiple channels having first, second, third and fourth channels. The inner button is inserted within the outer shell. The inner button includes a tab and a contact component. The tab moves within the multiple channels. When the tab is within the first channel, the inner button is in a first position and contact component is positioned over a first contact of the information handling system. When the tab is within the third channel, the inner button is in a second position and the contact component is positioned over a second contact of the information handling system.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Inventors: Jer-Yo Lee, Chun-Ting Lu, Cheng-Hsiang Chuang
  • Publication number: 20230386765
    Abstract: A multiple function button for an information handling system includes an outer button and an inner button. The outer button includes a first contact component positioned over a first contact of the information handling system. The first contact is associated with a first operation within the information handling system. The inner button is inserted within the outer button and includes a second contact component. The second contact component is positioned over a second contact of the information handling system, which in turn is associated with a second operation within the information handling system.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Inventors: Jer-Yo Lee, Chun-Ting Lu, Cheng-Hsiang Chuang
  • Publication number: 20200001739
    Abstract: A method of information provision is implemented by an electric carrier system which includes an electric carrier device storing a carrier identifier and carrier information, a power supply device providing electrical energy to the electric carrier device, and storing reference carrier identifiers and battery information, and an electronic device communicable with the electric carrier device and a server. The method includes: by the electric carrier device when in communication with the electric device, transmitting to the electronic device, integrated information including the carrier and battery information; and by the electronic device which is in communication with the server, transmitting the integrated information to the server.
    Type: Application
    Filed: April 24, 2019
    Publication date: January 2, 2020
    Inventors: Chun-Ting LU, Chia-Cheng TU, Te-Chuan LIU, Jen-Chiun LIN, Yuh-Rey CHEN, Po-Yu CHUANG
  • Patent number: 9570381
    Abstract: Described herein are semiconductor packages having an insulating layer and the manufacturing methods thereof, wherein semiconductor packages include a die pad; a plurality of leads surrounding the die pad, wherein each of the leads comprises an inner lead portion and an outer lead portion, and wherein at least one lead further comprises a trace portion; a chip disposed on the die pad and electrically connected to the leads; a molding compound encapsulating the chip, the inner lead portions and the trace portion, where the outer lead portions and a first surface of the trace portion are exposed from the molding compound; and an insulating layer covering the first surface of the trace portion.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: February 14, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Ting Lu, Chun-Hung Lin, Yi-Ting Chen
  • Publication number: 20160293531
    Abstract: Described herein are semiconductor packages having an insulating layer and the manufacturing methods thereof, wherein semiconductor packages include a die pad; a plurality of leads surrounding the die pad, wherein each of the leads comprises an inner lead portion and an outer lead portion, and wherein at least one lead further comprises a trace portion; a chip disposed on the die pad and electrically connected to the leads; a molding compound encapsulating the chip, the inner lead portions and the trace portion, where the outer lead portions and a first surface of the trace portion are exposed from the molding compound; and an insulating layer covering the first surface of the trace portion.
    Type: Application
    Filed: April 2, 2015
    Publication date: October 6, 2016
    Inventors: Chun-Ting LU, Chun-Hung LIN, Yi-Ting CHEN
  • Publication number: 20080308258
    Abstract: A micro-channel heat sink comprises an upper cover layer and a cooling layer. The cooling layer comprises at least one inlet fluid tank, a plurality of micro-channels, and at least one outlet fluid tank. The inlet fluid tank can store and deliver the working fluids, and the outlet fluid tank collects the heated working fluid flowing through the plurality of micro-channels. The plurality of micro-channels are disposed between the inlet fluid tank and the outlet fluid tank, wherein the cross sectional area of each of the micro-channels increases along the direction towards the outlet fluid tank.
    Type: Application
    Filed: May 16, 2008
    Publication date: December 18, 2008
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: CHIN PAN, PO CHANG LI, CHUN TING LU, KUN CHENG LIN
  • Patent number: 6812681
    Abstract: A digital dynamic trace adjustment pulse width modulate controller uses a core processing unit to receive a phase signal and outputs a pulse width modulate signal. It is observed that when the output voltage is rising or dropping then changing the pulse width modulate signal of the output end, the duty rate of the phase signal will be maintained at fifty percent degree.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: November 2, 2004
    Assignee: Silicom Technology Co., Ltd.
    Inventors: Chin-Tsai Hong, Chung-Fu Chou, Chun-Ting Lu, Thou-Vun Pang
  • Publication number: 20040207376
    Abstract: A digital dynamic trace adjustment pulse width modulate controller uses a core processing unit to receive a phase signal and outputs a pulse width modulate signal. It is observed that when the output voltage is rising or dropping then changing the pulse width modulate signal of the output end, the duty rate of the phase signal will be maintained at fifty percent degree.
    Type: Application
    Filed: April 16, 2003
    Publication date: October 21, 2004
    Inventors: Chin-Tsai Hong, Chung-Fu Chou, Chun-Ting Lu, Thou-Vun Pang
  • Publication number: 20040196670
    Abstract: This invention relates to a digital time mirrored pulse width modulate controller. The controller is electrically connected to a converter unit in which it comprises at least one comparator unit. The comparator unit outputs/inputs a voltage (Vo) and a preset voltage (Vset), and outputs a phase signal having low-level and high-level standards and a core digital processing unit, wherein the core digital processing unit outputs a pulse width modulate signal, through the units mentioned above. The characteristics of the invention can be summed up as follows: the elapsed time of the phase signal in high-level and in low-level is equal, and the root mean square of the output voltage in converter unit is equal to the preset voltage (Vset).
    Type: Application
    Filed: April 3, 2003
    Publication date: October 7, 2004
    Inventors: Chin-Tsai Hong, Chung-Fu Chou, Chun-Ting Lu, Thou-Vun Pang