Abstract: A method for fabricating a semiconductor device is provided. The method includes forming an alignment mark in a material layer, wherein the alignment mark has a step sidewall in the material layer, and the step sidewall of the alignment mark has a floor surface portion; forming a feature material over the material layer; and performing a planarization process at least on the feature material, wherein the planarization process stops at a level higher than the floor surface portion of the step sidewall of the alignment mark.

Abstract: The disclosure provides a push-type travel cup including a cup body, a cover assembly disposed on the cup body, a water channel disposed on the cup body, and a switch assembly disposed on the cover assembly. The cover assembly includes an inner cover and an outer cover covering the inner cover, and the outer cover is movable up and down with respect to the inner cover. The switch assembly includes a first support rod, a second support rod, a first magnet, and a second magnet. The outer cover includes a water outlet configured to communicate with the water channel; the first support rod is fixedly disposed on the inner cover, and the first magnet is disposed on one end of the first support rod; the second support rod is fixedly disposed on the outer cover, and the second magnet is disposed on one end of the second support rod.

Abstract: In some embodiments, a method processes a first packet and generates a first copy of the first packet as a second packet. The method sends second copies of the first packet to a first group of multiple destinations defined by a first address. Also, the method sends the second packet to an interface with a loopback function. The interface recirculates the second packet for further processing. The second packet is processed where the second packet is assigned a destination of a second address. Then, the method sends copies of the second packet to a second group of multiple destinations defined by the second address.

Abstract: Provided are an electrodeposited copper foil, a current collector, an electrode, and a lithium-ion secondary battery comprising the same. The electrodeposited copper foil has a deposited side and a drum side opposite the deposited side. In a first aspect, ?RS between the deposited side and the drum side is at most about 95 MPa, and the deposited side exhibits a Vv in a range from about 0.15 ?m3/?m2 to about 1.35 ?m3/?m2. In a second aspect, the deposited side has a Sku of about 1.5 to about 6.5 and the deposited side exhibits a Vv in a range from about 0.15 ?m3/?m2 to about 1.35 ?m3/?m2. The characteristics are beneficial to improve the quality of the electrodeposited copper foil, thereby extending the charge-discharge cycle life of a lithium-ion secondary battery comprising the same.

Abstract: A method for generating light is provided. The method further includes measuring a period of time during which one of targets from a fuel target generator passes through two detection positions. The method also includes exciting the targets with a laser generator so as to generate plasma that emits light. In addition, the operation of exciting the targets with the laser generator includes: irradiating a pre-pulse laser on the targets to expand the targets; detecting conditions of expanded targets; and adjusting at least one parameter of the laser generator according to the measured period of time and the conditions when the measured period of time is different from a predetermined value. The parameter of the laser generator which is adjusted according to the measured period of time includes a frequency for generating a laser for illuminating the targets.

Abstract: A movable and reconfigurable staircase. The stairs can be configured as a straight stair, a circular stair, or a combination stair. The stairs can be placed in a stored configuration as well.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate, patterning the first IMD layer to form first IMD patterns on the substrate, a trench surrounding the first IMD patterns, and a second IMD pattern surrounding the trench, forming a metal layer in the trench to surround the first IMD patterns, forming a second IMD layer on the first IMD patterns, the metal layer, and the second IMD pattern, and forming via conductors in the second IMD layer. Preferably, the via conductors not overlapping the first IMD patterns.

Abstract: The structure of a semiconductor device with an array of bioFET sensors, a biometric fingerprint sensor, and a temperature sensor and a method of fabricating the semiconductor device are disclosed. A method for fabricating the semiconductor device includes forming a gate electrode on a first side of a semiconductor substrate, forming a channel region between source and drain regions within the semiconductor substrate, and forming a piezoelectric sensor region on a second side of the semiconductor substrate. The second side is substantially parallel and opposite to the first side. The method further includes forming a temperature sensing electrode on the second side during the forming of the piezoelectric sensor region, forming a sensing well on the channel region, and binding capture reagents on the sensing well.

Abstract: A DC-DC converter including a first power supply including a first converter outputting a first power voltage, a first sensor detecting a panel current from an output of the first converter; and a first output group including a plurality of inverting converters outputting a second power voltage based on the panel current; a second power supply including a second converter outputting the first power voltage, and a second output group including a plurality of inverting converters outputting the second power voltage based on the panel current; and a first phase controller controlling operations of the inverting converters included in each of the first and second output groups based on the detected panel current. The second power supply operates when the panel current exceeds a predetermined enable value.

Abstract: The present invention relates to a method for analyzing a sample. In particular, the present invention relates to a method for analyzing a sample and a method for correcting a raw data set of an amplification reaction. The present invention for analyzing a sample prevents from determining cycles based on false signals usually observed in a multitude of reactions and processes, thereby much more accurately obtaining information for analyzing a sample.

Abstract: A method and apparatus are disclosed from the perspective of a UE (User Equipment). In one embodiment, the method includes the UE being configured with a control resource set (CORESET). The method further includes the UE receiving a Downlink Control Information (DCI) on the CORESET, wherein an index is included in the DCI and the index indicates a time domain resource allocation pattern. The method also includes the UE receiving data in Orthogonal Frequency Division Multiplexing (OFDM) symbols determined according to the time domain resource allocation pattern, wherein a range of the time domain resource allocation pattern starts from the first OFDM symbol of the CORESET or after an offset from the first OFDM symbol of the CORESET, and the range of the time domain resource allocation pattern may end across a slot boundary.

Abstract: Handling frequently accessed pages is disclosed. An indication is received of a stalling event caused by a requested portion of memory being inaccessible. It is determined that the requested portion of memory is a frequently updated portion of memory. The stalling event is handled based at least in part on the determination that the requested portion of memory is a frequently updated portion of memory.

Abstract: A semiconductor device includes a buried logic conductor (BLC) CFET, the BLC CFET including: relative to a first direction, first and second active regions arranged in a stack according to CFET-type configuration; first and second contact structures correspondingly electrically coupled to the first active region; third and fourth contact structures correspondingly electrically coupled to the second active region; a first layer of metallization over the stack which includes alpha logic conductors configured for logic signals (alpha logic conductors), and power grid (PG) conductors, the alpha logic and PG conductors being non-overlapping of each other; and a layer of metallization below the stack which includes beta logic conductors which are non-overlapping of each other; and wherein, relative to a second direction, each of the alpha logic, PG and beta logic conductors at least partially overlap one or more of the first, second, third and fourth contact structures.

Abstract: A rechargeable battery includes: an electrode assembly including a first electrode, a second electrode, a separator between the first and second electrodes, and first and second electrode tabs respectively coupled to the first and second electrodes; a case accommodating the electrode assembly and coupled to the first electrode tab; and a cap assembly sealing an opening in the case. The cap assembly includes: a cap plate covering the opening in the case; and a terminal plate coupled to the cap plate. The terminal plate includes: a flange portion coupled to and electrically insulated from the cap plate; and a tab connecting portion protruding from the flange portion toward the electrode assembly and extending through a terminal opening in the cap plate to be coupled to the second electrode tab. The terminal plate has a flat outer surface, and the tab connecting portion has a flat inner surface.

Abstract: A chassis for electronic equipment, comprising a front panel, a slot disposed in the front panel and a first computer card latch disposed in the slot, the first computer card latch configured to hold a computer card having a first predetermined height.

Abstract: The present invention features processes for preparing compounds, such as (R)-1-(2,2-difluorobenzo[d][1,3]dioxol-5-yl)-N-(1-(2,3-dihydroxypropyl)-6-fluoro-2-(1-hydroxy-2-methylpropan-2-yl)-1H-indol-5-yl)cyclopropanecarboxamide (Compound 1), useful for treating CFTR mediated diseases such as cystic fibrosis.

Abstract: An automatic nut internal thread quality tester is provided. The automatic nut internal thread quality tester includes a blanking module, a clamping module, a push rod module, a thread gauge driving module, and an axial pushing module. The blanking module is configured to control the nuts to be tested be blanked in series. The clamping module is configured to clamp the to-be-tested nut. The push rod module is configured to push the to-be-tested nut into the clamping module and restrict the blanking. A thread gauge of the thread gauge driving module is driven by a motor to detect the to-be-tested nut. When a torque measured by a torque sensor is greater than a threshold value, the motor reverses the thread gauge and the axial pushing module drives the clamping module away from the thread gauge.

Abstract: Embodiments of this application disclose methods, systems, and devices for video synthesis. In one aspect, a method comprises obtaining a plurality of frames corresponding to source image information of a first to-be-synthesized video, each frame of the source image information. The method also comprises obtaining a plurality of frames corresponding to target image information of a second to-be-synthesized video. For each frame of the plurality of frames corresponding to the target image information of the second to-be-synthesized video, the method comprises fusing a respective source image from the first to-be-synthesized video, a corresponding source motion key point, and a respective target motion key point corresponding to the frame using a pre-trained video synthesis model, and generating a respective output image in accordance with the fusing. The method further comprises repeating the fusing and the generating steps for the second to-be-synthesized video to produce a synthesized video.

Abstract: An optical calibration tool includes a first body, a light emitter, a light receiver, a second body, and a light reflecting member. The first body has a first engaging port and a second engaging port. The light emitter and the light receiver are disposed in the first body. The second body has a third engaging port and a channel communicated with each other. The third engaging port is configured to selectively engage one of the first engaging port and the second engaging port. When the third engaging port is engaged with the first engaging port, the light emitter is optically coupled to the light reflecting member. When the third engaging port is engaged with the second engaging port, the light receiver is optically coupled to the light reflecting member.

Abstract: Mitochondria modified by a targeting protein, according to one embodiment of the present invention, can be effectively delivered to a target. In addition, when a protein of interest bound to the modified mitochondria is delivered into a cell, various activities can be exhibited. The modified mitochondria can effectively cause cancer tissue death, and thus can also be used as an anticancer agent. Furthermore, various activities are exhibited according to a protein of interest loaded on modified mitochondria, and thus the modified mitochondria can be applied in the treatment of various diseases. Additionally, a fusion protein comprising a protein of interest and a fusion protein comprising a targeting protein, according to one embodiment of the present invention, can be used in order to modify mitochondria. Moreover, mitochondria modified with the fusion proteins exhibits various effects in a target cell.