Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Abstract: Provided are co-crystals of a sodium benzoate compound and a co-former compound of Formula (I) Also provided herein are methods of preparing the co-crystals and uses thereof in treating and/or reducing the risk for a neuropsychiatric disorder (e.g., schizophrenia, psychotic disorders, depressive disorders, or Alzheimer's disease) or a glucose or lipid metabolic disorder (e.g., obesity, diabetes, hypercholesterolemia, hypertension, or hyperlipidemia).

Abstract: A pixel circuit includes a light-emitting device, a first transistor, a second transistor, a first capacitor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor and the fourth transistor are controlled by a light-emitting signal. The third transistor and the fifth transistor are controlled by a scan signal. The light-emitting device, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are serially connected between a system high voltage and a system low voltage. The third transistor is coupled between a data signal and a control terminal of the first transistor. The first capacitor is coupled between a control terminal and a downstream terminal of the second transistor. The fifth transistor is coupled between the downstream terminal of the second transistor and a charging reference voltage. A current of the charging reference voltage is less than a current of the system low voltage.

Abstract: A tire that can attach and detach and that can prevent splash when running a wet road and cool discharging a heat is provided. The tire having a tread and a shoulder portion connected to the tread includes a protector portion provided in a circumferential direction at a side surface of the shoulder portion and in which a plurality of penetration portions are formed at a predetermined gap in a length direction; a plurality of protruding portions provided in the protector portion and formed at a predetermined gap in a length direction of the protector portion; and a plurality of installation grooves formed at a side surface of the shoulder portion such that the protruding portion attaches or detaches when the protruding portion enters or discharges.

Abstract: The present technology is generally directed to non-perpendicular connections between coke oven uptakes and a hot common tunnel, and associated systems and methods. In some embodiments, a coking system includes a coke oven and an uptake duct in fluid communication with the coke oven. The uptake duct has an uptake flow vector of exhaust gas from the coke oven. The system also includes a common tunnel in fluid communication with the uptake duct. The common tunnel has a common flow vector and can be configured to transfer the exhaust gas to a venting system. The uptake flow vector and common flow vector can meet at a non-perpendicular interface to improve mixing between the flow vectors and reduce draft loss in the common tunnel.

Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

Abstract: This invention discloses a DRAM cell includes an asymmetric transistor coupled to a capacitor. The asymmetric transistor includes a drain region extending upward from an isolator region; a gate region extends upward from a gate dielectric or the isolator; a source region of asymmetric transistor extends upward from a first portion of an isolating layer. The upward extending directions of the drain region, the gate region, and the source region are perpendicular or substantially perpendicular to an original silicon surface. Moreover, the capacitor is partially formed in a concave and the isolating layer is positioned in the concave. The capacitor extends upward from a second portion of the isolating layer. The upward extending directions of the upright portion of the capacitor electrode, the third portion of the insulating layer and the counter electrode are perpendicular or substantially perpendicular to the original silicon surface.

Abstract: The disclosure provides an image identifying method and an image identifying device. The method includes: retrieving a first computer tomographic (CT) image including a plurality of first pixels; retrieving a plurality of second pixels from the first pixels, and generating a second CT image based on the second pixels; performing a contrast enhancement algorithm on the second CT image to adjust a contrast of the second CT image; identifying a first image region in the second CT image to generate a third CT image, wherein the first image region includes a first object; dividing the third CT image into a plurality of sub-images, and only reserving a specific image region corresponding to the first object in each sub-image; combining the sub-images into a fourth CT image; and identifying an object type of the first object based on the fourth CT image.

Abstract: A memory data management method includes the following steps reading a plurality of data of a plurality of memory cells of a memory block; determining whether error bits of the data exceed an error correction code (ECC) threshold; if the error bits of the data exceed the ECC threshold, a programming process being executed to increase a first threshold voltage of a first state data of the data for exceeding a first threshold, to increase a second threshold voltage of a second state data of the data for exceeding a second threshold, and to increase a third threshold voltage of a third state data of the data for exceeding a third threshold.

Abstract: A display device includes a display panel and an optical element. The display panel includes a non-display area and a display area. The optical element is disposed corresponding to the display panel and includes a main body portion and a positioning portion connected to the main body portion. The main body portion includes a first part corresponding to the non-display area and a second part corresponding to the display area. The first part has a first opening disposed adjacent to the positioning portion.

Abstract: A method and a system for generating dynamic map information with environment information are provided, wherein the system includes a cloud server, multiple relay hosts distributed around the environment and multiple vehicle devices each installed respectively in different vehicles. Each vehicle device includes a LiDAR sensor and a camera for sensing the environment to respectively generate point cloud data and image data. When the point cloud data from different vehicles are transmitted to a neighboring relay host, the relay host performs a multi-vehicle data integration mode to merge the point cloud data and obtain 3D coordinates information of objects in the environment according to the merged data. Based on the 3D coordinates information of objects, the cloud server generates and transmits dynamic map information to the vehicles. By sharing sensing data of different vehicles, the sensing area of each vehicle is expanded to mitigate dark zones or blind zones.

Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.

Abstract: A slide rail mechanism includes a rail member, a supporting member, a first bracket and a fastening member. The rail member includes an upper wall, a lower wall and a longitudinal wall connected between the upper wall and the lower wall. The supporting member and the rail member are capable of moving relative to each other along a longitudinal direction. The supporting member includes an upper supporting portion, a lower supporting portion and a longitudinal portion connected between the upper supporting portion and the lower supporting portion. The first bracket and the supporting member are capable of moving relative to each other along the longitudinal direction. The fastening member is capable of in one of a first state and a second state relative to the first bracket.

Abstract: An electronic device includes a first substrate, a first conductive layer, a plurality of first electrode pads, a plurality of first light-emitting units, a plurality of first signal pads and a conductive structure. The first conductive layer is disposed on the first substrate. The first electrode pads are disposed on the first conductive layer. The first light-emitting units overlap and are disposed on the first electrode pads. The first light-emitting units are electrically connected to the first electrode pads respectively. The first signal pads are disposed on the first conductive layer and electrically connected to the first conductive layer. The conductive structure is disposed on the first signal pads, and at least two of the first signal pads are electrically connected to each other through the conductive structure.

Abstract: A system and method of diagnosing gastrointestinal neoplasm or pathologies in an endoscopy system including an endoscopy system display for displaying an image enhanced endoscopy (IEE) image. The method includes randomly generating training image samples with or without cancer region(s) by an adversarial network (AN) including collecting endoscopic training images (T1) and automatically generating a realistic IEE image as a new training image sample (T2) using a generator network in the AN from a generated segmentation map; using a prediction network (L1PN) to learn a level 1 prediction result being a cancerous probability of an IEE image from the collected T1 and T2; using a prediction network (L2PN) to learn a level 2 prediction result being detected cancerous region(s) of an IEE image; and predicting the level 1 result and the level 2 result for an IEE image using the L1PN and the L2PN and without using the AN.

Abstract: An antenna structure includes a signal source, four transmission lines, and four radiation elements. The radiation elements are coupled through the transmission lines to the signal source, respectively. Each of the radiation elements includes a loop structure, a first connection element, and a second connection element. The loop structure has a first inner edge and a second inner edge which are opposite to each other. A looped region is formed between the first inner edge and the second inner edge. The looped region has first and second sides. The first connection element extends across the first side of the looped region. The first connection element is coupled between the first inner edge and the second inner edge. The second connection element extends across the second side of the looped region. The second connection element is coupled between the first inner edge and the second inner edge.

Abstract: A circuit selector of embedded magnetoresistive random access memory (EMRAM) includes a transistor comprising a source/drain terminal coupled to a first magnetic tunneling junction (MTJ) and a second MTJ, a gate terminal, and a drain/source terminal coupled to a voltage source. Preferably, the first MTJ includes a first free layer, a first barrier layer, and a first pinned layer, in which the first free layer is coupled to the source/drain terminal and the first pinned layer is coupled to a first circuit. The second MTJ includes a second free layer, a second barrier layer, and a second pinned layer, in which the second pinned layer is coupled to the source/drain terminal and the second free layer is coupled to a second circuit.

Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.

Abstract: A random bit stream generator which includes a pseudo-random bit stream generator and a multi-stage noise shaping (MASH) delta-sigma modulator is introduced. The pseudo-random bit stream generator may generate a first random bit stream according to a first clock signal. The MASH delta-sigma modulator is coupled to the first random bit stream generator to receive the first random bit stream and output a second random bit stream according to the first random bit stream and a second clock signal. A frequency of the second clock signal is greater than a frequency of the first clock signal, and the random bit stream has bell-shaped distribution. A method of generating a random bit stream having bell-shaped distribution adapted to a random bit stream generator is also introduced.

Abstract: An input device includes a wheel supporting structure, a scroll wheel, a hook part, a linking part, and a switching mechanism. The scroll wheel is rotatably supported by the wheel supporting structure, is exposed from the input device, and has a rotary shaft with a plurality of toothed slots thereon. The hook part is disposed biased on the wheel supporting structure to selectively engage with the toothed slots. The linking part is pivotally connected to the wheel supporting structure. The switching mechanism includes an abutting part and a switching part. The abutting part abuts against the linking part. The switching part is coupled to the abutting part. Therein, the switching mechanism is operable to move the abutting part through the switching part to rotate the linking part to abut against and move the hook part to disengage from the toothed slots.