Patents by Inventor Chun To

Chun To has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for providing control resource set configuration in a wireless communication system
    Patent number: 10951359
    Abstract: Methods and apparatuses for providing control resource set configuration in a wireless communication system are disclosed herein. In one method, a network node transmits a signal indicating at least a first duration and a bit map, wherein the first duration is time duration of a control resource set (CORESET) and the bit map indicates first symbol(s) of monitoring occasion(s) of the CORESET within a slot, and wherein a set of bit position indicates value one in the bit map. The network node is not allowed to transmit the signal such that an interval between two bit positions in the set in the bit map is smaller than a second duration.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: March 16, 2021
    Assignee: ASUSTek Computer Inc.
    Inventors: Chun-Wei Huang, Ko-Chiang Lin
  • Apparatus and method for manufacturing bio emulsion fuel using vegetable oil
    Patent number: 10947469
    Abstract: A bio emulsion fuel manufacturing apparatus and method using vegetable oil is provided, including an oil tank unit configured to refine a vegetable oil introduced from an oil inlet by using a coagulant agent and a centrifugal decanter; a water tank unit configured to pretreat a water introduced from a water inlet by using a water tank catalyst; a mixed oil unit connected to the oil tank unit and the water tank unit, and configured to produce a mixed oil by using an inline mixer; and an ionization catalyst unit connected to the mixed oil unit and configured to convert the mixed oil to a bio emulsion fuel by using an ionization catalyst group.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: March 16, 2021
    Inventors: James Chun Koh, Shinji Hasegawa
  • Battery safety identifying method and method for setting hazard levels of battery internal short circuit and warning system using the same
    Patent number: 10948544
    Abstract: A battery safety identifying method is provided. The method includes the following steps. A voltage drop and a voltage drop rate are detected when a battery is abnormal. A duration time of the voltage drop and a voltage recovery ratio are detected when the battery is abnormal. A surface temperature or a temperature rise rate is detected when the battery is abnormal. A plurality of hazard levels of battery abnormality and at least one protection mechanism are set according to the voltage drop, the voltage drop rate, the voltage recovery ratio and the surface temperature or the temperature rise rate.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 16, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chein-Chung Sun, Chun-Hung Chou, Deng-Tswen Shieh, Che-Wei Chu
  • Fabrication method of packaging structure
    Patent number: 10950525
    Abstract: Method for fabricating A packaging structure is provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure includes a passivation layer on the base substrate and exposing the solder pad body region and the trench region. The packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. The packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 16, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Li Zhong Jin, Li Hui Lu, Chun Chao Fei, Po Yuan Chiang, Ya Ping Wang
  • Pixel circuit, pixel circuit driving method, and display device thereof
    Patent number: 10950163
    Abstract: A pixel circuit includes a driving circuit, a lighting element, and multiple switching circuits. The driving circuit is configured to provide a driving current to a first node. A first terminal of the lighting element is coupled with a second node. A second terminal of the lighting element is configured to receive a system low voltage. The multiple switching circuits are coupled between the first node and the second node in a parallel connection, and configured to correspondingly receive multiple emission control signals and at least one grayscale control signal. During each frame, the multiple emission control signals provide multiple pulses, and the multiple pulses do not mutually overlapping in time sequence, so that the multiple switching circuits selectively couple the first node to the second node according to the multiple pulses and the at least one grayscale control signal.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: March 16, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Po-Chun Lai, Wei-Ting Wu, Syuan Shih, Wan-Lin Chen, Ming-Yuan Tang, Wei-Hsuan Chang, Yung-Chih Chen
  • Thermal-curable adhesive composition and adhesive sheet
    Patent number: 10947417
    Abstract: The instant disclosure provides a thermal-curable adhesive composition and adhesive sheet. The thermal-curable adhesive composition has a rate of change of adhesion ranging from 80% to 98% and defined by the following equation: V=[(V0?V1)/V0]×100, wherein V is the rate of change of adhesion of the thermal-curable adhesive composition, V0 is the adhesion of the thermal-curable adhesive composition under room temperature, and V1 is the adhesion of the thermal-curable adhesive composition after being heated to a predetermined temperature then cooled to the room temperature.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 16, 2021
    Assignee: TAIMIDE TECH. INC.
    Inventors: Chih-Wei Lin, Chun-Ting Lai
  • Heterojunction semiconductor device for reducing parasitic capacitance
    Patent number: 10950524
    Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a first source pad, and a first drain pad. The source electrode, the drain electrode, and the gate electrode are disposed on an active region of the active layer. The first insulating layer is disposed on the source electrode, the drain electrode, and the gate electrode. The first source pad and the first drain pad are disposed on the first insulating layer and the active region. The first source pad includes a first source body and a first source branch. The first source branch is electrically connected to the first source body and disposed on the source electrode. The first drain pad includes a first drain body and a first drain branch. The first drain branch is electrically connected to the first drain body and disposed on the drain electrode.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 16, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Li-Fan Lin, Chun-Chieh Yang
  • Method and device for determining action or action part
    Patent number: 10948979
    Abstract: The present application provides methods and devices for determining an action or an action part, and generally relates to the field of wearable devices. A method disclosed herein comprises: in response to detecting a motion of a first part of a body of a user, acquiring, using a photoelectric sensor, target Doppler measurement information of the first part or a second part corresponding to the first part; determining target velocity related information corresponding to the target Doppler measurement information; and determining the first part or the action according to the target velocity related information and reference information, wherein the target velocity related information comprises target blood flow velocity information or target blood flow information. The methods and devices provide a new scheme for recognizing an action and/or an action part.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 16, 2021
    Assignee: BEIJING ZHIGU RUI TUO TECH CO., LTD.
    Inventors: Yuanchun Shi, Yuntao Wang, Chun Yu, Lin Du
  • Heat source device and substrate processing apparatus including same
    Patent number: 10950473
    Abstract: The present disclosure relates to a heat source device and a substrate processing apparatus including same. The substrate processing apparatus includes: a chamber having an inner space in which a substrate is processed; a substrate support provided inside the chamber and supporting the substrate; and a heat source device including a supporting body provided in at least one side of the chamber, and a heat source unit provided parallel to the substrate support so as to heat the substrate. The heat source unit is provided with a first light transmission conduit connected to the supporting body, a heat source provided inside the first light transmission conduit, and a first cooling conduit provided inside the first light transmission conduit while being spaced apart from the heat source, and having a first spraying hole to spray a cooling gas. The temperature of the substrate may be efficiently controlled.
    Type: Grant
    Filed: February 24, 2018
    Date of Patent: March 16, 2021
    Inventors: Ji Young Jeong, Kyung Chun Jung
  • Memory device and operating method thereof that reduce off current to reduce errors in reading and writing data which have plurality of memory cell blocks and a source voltage generator
    Patent number: 10950290
    Abstract: A memory device is provided. The memory device includes a plurality of memory cell blocks and a source voltage generator. Each of the memory cell blocks has at least one memory cell. The source voltage generator is coupled to the plurality of memory cell blocks and configured to cause a source voltage of the memory cell block to be a first voltage according to that a memory cell in each of the memory cell blocks is in a selected state and cause a source voltage of the memory cell block to be a second voltage according to that all memory cells in each of the memory cell blocks are in an unselected state, wherein an absolute value of the first voltage is less than an absolute value of the second voltage. In addition, an operating method of the memory device is also provided.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: March 16, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Chang Lu, Wen-Jer Tsai
  • Handling various scenarios where an email recipient is not available
    Patent number: 10951565
    Abstract: A method for sending a plurality of alternate contact information associated with an online communication system. The method may include receiving an electronic message associated with the online communication system, wherein the electronic message is addressed to a recipient from a sender. The method may also include identifying a recipient inbox using a plurality of directory information associated with the received electronic message. The method may further include determining the identified recipient inbox satisfies at least one of a plurality of alternate contact criteria. The method may also include transmitting a plurality of alternate recipient contact information within a simple message transfer protocol (SMTP) response to the sender based on the plurality of determined alternate contact criteria being satisfied.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Wai Man Lee, Hon Chung Tang, Ka Chun Wong, Wing Kong Yip
  • Reducing chemoepitaxy directed self-assembled defects
    Patent number: 10949601
    Abstract: A method for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, the method comprising expanding a shape of the guiding pattern by a predetermined distance in both lateral directions to form a fin keep mask, where the fin keep mask comprises a stand-alone mask.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Kafai Lai, Chi-Chun Liu, Ananthan Raghunathan, Hsinyu Tsai
  • LED display with electroluminescent components
    Patent number: 10950167
    Abstract: A light-emitting diode (LED) includes a first electroluminescent (EL) component, a second EL component, a first segment electrode, a second segment electrode, and a first common electrode. The first segment electrode is electrically connected to the first EL component. The second segment electrode is electrically connected to the second EL component. The first common electrode has a first branch and a second branch which extend along a first direction and are arranged in a second direction different than the first direction. The first branch is located between the second branch and either of the first and second EL components, and the first and second branches are electrically connected to the first and second EL components, respectively.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 16, 2021
    Assignee: Solomon Systech (Shenzhen) Limited
    Inventors: Wing Chi Stephen Chan, Chi Wai Lee, Pie Chih Ke, Chun Hung Lai
  • Merged source/drain features
    Patent number: 10950730
    Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
  • High-density semiconductor device
    Patent number: 10950456
    Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Hsin-Chih Chen, Shi Ning Ju, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Cheng Lin, Wei-Liang Lin
  • AT commands for 5G QoS management
    Patent number: 10952094
    Abstract: A method of defining ATtention (AT) commands for 5G QoS management is proposed. AT commands for modifying PDU sessions, creating and modifying QoS flows and QoS rules, and for querying QoS flow and QoS rule parameters are defined for 5G networks. Specifically, the AT command can be a set command for triggering a PDU session modification procedure and thereby creating and modifying QoS flows and QoS rules. For example, AT command +C5GQOS is introduced for creating and modifying QoS flows, AT command +C5GQOSRDP is introduced for retrieving QoS flow parameters, AT command +CGTFT can be reused for creating and modifying QoS rules, and AT command +CGTFTRDP can be reused for retrieving QoS rule parameters.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: March 16, 2021
    Assignee: MediaTek INC.
    Inventors: Chien-Chun Huang-Fu, Chi-Hsien Chen
  • Method of fabricating a semiconductor device including vertical-type field effect transistors
    Patent number: 10950724
    Abstract: A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeoncheol Heo, Sharma Deepak, Kwanyoung Chun
  • Surface mounted fuse device having positive temperature coefficient body
    Patent number: 10950372
    Abstract: A PPTC device including a PPTC body, a first electrode, disposed on a first side of the fuse component, a second electrode, disposed on a second side of the PPTC body, wherein the PPTC body comprises a polymer matrix and a conductive filler.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: March 16, 2021
    Assignee: Littelfuse, Inc.
    Inventors: Zhiyong Zhou, Jianhua Chen, Chun-Kwan Tsan
  • BIOFET WITH INCREASED SENSING AREA
    Publication number: 20210072181
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure, an isolation layer, an interface layer in an opening of the isolation layer, and a metal crown structure over the interface layer. The interface layer and the metal crown structure are disposed on opposite side of the transistor from a gate structure.
    Type: Application
    Filed: November 2, 2020
    Publication date: March 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wen CHENG, Yi-Shao LIU, Fei-Lung LAI
  • OPERATING CIRCUIT
    Publication number: 20210075215
    Abstract: An operating circuit is provided. A first N-type transistor determines whether to turn the path between a core circuit and a ground terminal on or off according to the voltage level of a specific node. An electrostatic discharge (ESD) protection circuit is coupled between an input/output pad and the core circuit to prevent an ESD current from passing through the core circuit. The ESD protection circuit includes a detection circuit and a releasing element. The detection circuit determines whether there is an ESD event at the input/output pad and generates a first detection signal according to the detection of the ESD event at the input/output pad. The releasing element provides a release path according to the first detection signal to release the ESD current. A control circuit controls the voltage level of the specific circuit according to the first detection signal.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Li-Fan Chen, Ching-Ho Li, Ting-You Lin, Chun-Chih Chen, Kai-Chieh Hsu, Chih-Hsuan Lin, Yu-Kai Wang