Abstract: An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably couple with an MDI circuit to conduct data communication with a respondent-side circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably conduct a physical coding operation according to the instruction of the processing circuit to control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit.

Abstract: An optical device includes a photoelectric conversion layer, an anti-reflection layer, an underlying layer, a bottom meta layer, and a top meta layer. The photoelectric conversion layer includes a plurality of photodiodes. The anti-reflection layer is disposed on the photoelectric conversion layer. The underlying layer is disposed on the anti-reflection layer. The bottom meta layer is disposed on the underlying layer and includes a plurality of bottom meta units and a filling between the bottom meta units, in which the filling is continuously extend from the underlying layer, and a material of the filling is the same as a material of the underlying layer. The top meta layer is disposed above the bottom meta layer and includes a plurality of top meta units and a plurality of air recesses, in which the plurality of air recesses are respectively disposed between two adjacent top meta units.

Abstract: Abstract of Disclosure A control gate is formed on the substrate. A source diffusion region is formed in the substrate and on a first side of the control gate. A select gate is formed on the source diffusion region. The select gate has a recessed top surface. A charge storage structure is formed under the control gate. A first spacer is formed between the select gate and the control gate and between the charge storage structure and the select gate. A wordline gate is formed on a second side of the control gate opposite to the select gate. A second spacer is formed between the wordline gate and the control gate. A drain diffusion region is formed in the substrate and adjacent to the wordline gate.

Abstract: A method includes depositing an epitaxial stack over a substrate, the epitaxial stack comprising alternating first semiconductor layers and second semiconductor layers, wherein the first semiconductor layers comprise a different semiconductor composition from that of the second semiconductor layers; forming a dielectric wall in the epitaxial stack; removing a first subset of the first semiconductor layers on a first side of the dielectric wall, while leaving a first subset of the second semiconductor layers on the first side of the dielectric wall; removing a second subset of the second semiconductor layers on a second side of the dielectric wall, while leaving a second subset of the first semiconductor layers on the second side of the dielectric wall; forming a first gate structure around the first subset of the second semiconductor layers; and forming a second gate structure around the second subset of the first semiconductor layers.

Abstract: An asset manager controls power distribution within an aggregated distributed energy resources system (“DERs system”) having a plurality of assets. The asset manager is configured to operate with a given asset. As such, the asset manager has 1) an interface to receive asset information relating to the given asset and to communicate with another asset manager in the DERs system, and 2) a function generator configured to produce a local cost function using data relating to the given asset only. The local cost function represents a portion of a system cost function for the DERs system. The asset manager also has 3) a controller configured to use the local cost function for the given asset to manage operation of the given asset in the DERs system. In addition, the controller also is configured to determine, using the local cost function, an operating point for the given asset.

Abstract: A display panel includes a substrate, first, second, and third data lines, scan lines, a first active device, a second active device, and pixel electrodes. The first and the third data lines have a first polarity. The second data line has a second polarity. The first polarity is different from the second polarity. A source electrode of the first active device disposed between the first data line and the second data line is electrically connected to the first data line. An extension region of the semiconductor pattern of the first active device extends toward and overlaps the second data line. A source electrode of the second active device disposed between the second data line and the third data line is electrically connected to the second data line. An extension region of the semiconductor pattern of the second active device extends toward and overlaps the third data line.

Abstract: A memory device includes a memory cell array having a plurality of memory blocks therein, including a target memory block. A voltage generator is provided, which is configured to generate an erase voltage and row line voltages, which are provided to the target memory block upon which an erase operation is to be performed. Control logic is provided, which is configured to control the memory cell array and the voltage generator. In addition, during operation, the erase voltage is provided to at least one of a bitline or a common source line associated with the target memory block, and a gate line of a transistor provided with the erase voltage is precharged before the erase voltage is provided to the at least one of the bitline or the common source line of the target memory block.

Abstract: Proposed are a method and device for transmitting a feedback frame in a wireless LAN system. Specifically, a reception STA receives an NDPA frame from a transmission STA. The reception STA receives an NDP frame from the transmission STA. The reception STA transmits a feedback frame to the transmission STA through a predetermined bandwidth on the basis of the NDPA frame and the NDP frame. The NDPA frame includes information on a portion of a band. The information on the portion of the band includes a bitmap comprising first to ninth bits. The first bit includes information on a channel unit for requesting feedback information.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) having a portion within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. The epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. A lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer.

Abstract: The present invention provides a high electron mobility transistor, which includes a substrate, a buffer layer, a gallium nitride layer, a two-dimensional material structure, a covering layer, a drain, a source and a gate. The buffer layer is located on the substrate. The gallium nitride layer is located on the buffer layer and forms a channel layer. The two-dimensional material structure is located on the channel layer. The covering layer partially covers the two-dimensional material structure. The drain and the source are arranged on the two-dimensional material structure, and the gate is arranged on the covering layer.

Abstract: The present invention provides a high electron mobility transistor, which includes a substrate, a buffer layer, a channel layer, a first semiconductor epitaxial structure, a second semiconductor epitaxial structure, a drain, a source and a gate. The first semiconductor epitaxial structure is located on the channel layer and sequentially includes a first aluminum gallium nitride layer, a supply layer and a second aluminum gallium nitride layer, and the first semiconductor epitaxial structure is formed with a hollow part extending from a top surface of the second aluminum gallium nitride layer toward the channel layer. The second semiconductor epitaxial structure is located in the hollow part and sequentially includes an aluminum gallium nitride layer and a P-type gallium nitride layer. The drain and the source are respectively arranged on the second aluminum gallium nitride layer, and the gate is arranged on the P-type gallium nitride layer.

Abstract: A composition includes an active composition. The active composition includes a niobium-titanium oxide and a silicon active material, or includes a doped niobium-titanium oxide and the silicon active material. The niobium-titanium oxide includes niobium element, titanium element and oxygen element. The doped niobium-titanium oxide includes niobium element, titanium element and oxygen element.

Abstract: A micro light-emitting diode display is based on a conventional micro light-emitting diode display and includes at least one electrically conductive material layer or at least one functional material added to an encapsulation layer, so as to achieve antistatic effect. The micro light-emitting diode display solves the problem that the conventional micro light-emitting diode display is easily damaged by electrostatic breakdown.

Abstract: The present disclosure provides a structure of an ultraviolet light sensing-enhanced photodiode. The main structure of the photodiode includes a silicon photodiode and an infrared conversion layer formed on a surface that receives an ultraviolet light of the of the silicon photodiode. When the ultraviolet light irradiates on the ultraviolet light sensing-enhanced photodiode through the infrared conversion layer, the infrared conversion layer converts the ultraviolet light into an infrared light. The first portion of the infrared light is propagated to the silicon photodiode and then converted to a photoelectric current. The second portion of the infrared light is absorbed by the infrared conversion layer. An infrared reflection layer is also provided for reflecting the third portion of the infrared light that is originally escaped from the infrared reflection layer, and the third portion of the infrared light can be reflected into the silicon photodiode.

Abstract: A display device includes pixels, an image converter which generates a second image by correcting grayscales of a first logo in a first image for the pixels, and a data driver which provides data signals corresponding to the second image to the pixels. The image converter detects the first logo based on value and saturation of the first image, generates first map data corresponding to the first logo, and specifies pixels corresponding to the first logo based on the first map data.

Abstract: In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.

Abstract: Aspects of the present disclosure relate to encrypted data processing (EDAP). Encrypted data from a cache to be loaded into a register file can be accessed. The encrypted data can be decrypted to receive cleartext data. The cleartext data can be written to the register file. The cleartext data can be processed using at least one functional unit to receive cleartext computation results. The cleartext computation results can then be written back to the register file.

Abstract: A circuit carrier includes a substrate, a capacitive electrode layer, a plurality of metal pads and a plurality of bridges, and a plurality of conductive pillars. The capacitive electrode layer formed on a surface of the substrate and includes a plurality of first electrodes and a plurality of second electrodes. At least two of the first electrodes are connected to each other and be arranged across a die-bonding region of the substrate for separating at least two of the second electrodes that partially protrude from the die-bonding region to respectively form extensions. The metal pads and the bridges are formed on another surface of the substrate and are located outside of the die-bonding region. Each of the bridges connects two of the metal pads, and each of the conductive pillars is embedded in the substrate and connects one of the extensions and a corresponding one of metal pads.

Abstract: A method of forming an integrated circuit includes placing a first and a second standard cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height. Placing the first standard cell layout design includes placing a first set of pin layout patterns on a first layout level over a first set of gridlines, extending in a first direction, and having a first width in a second direction. Placing the second standard cell layout design includes placing a second set of pin layout patterns on the first layout level over a second set of gridlines, extending in the first direction, and having a second width in the second direction.