Patents by Inventor Chun Tsao
Chun Tsao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113345Abstract: A battery module and a short protection method thereof are provided. The battery module has a battery cell pack and a control circuit. The method includes: detecting a temperature of the battery cell pack as a battery cell temperature through the control circuit; determining whether the battery cell temperature shows a downward trend when the battery cell temperature is higher than a first predetermined temperature value; and deactivating the battery module when the battery cell temperature does not show the downward trend.Type: ApplicationFiled: May 23, 2023Publication date: April 4, 2024Applicant: ASUSTeK COMPUTER INC.Inventors: Chunyen Lai, Yu-Cheng Shen, Chun Tsao, Chaochan Tan, Huichuan Lo, Wen-Che Chung, Ming Hung Yao
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Publication number: 20240112851Abstract: A planar transformer includes a magnetic core assembly, at least one printed circuit board and at least one winding module. The magnetic core assembly includes a first magnetic core and a second magnetic core. The at least one printed circuit board is disposed between the first magnetic core and the second magnetic core. The printed circuit board includes a first winding. The at least one winding module is disposed between the first magnetic core and the second magnetic core. The winding module includes a second winding and a plastic molding layer. At least a portion of the second winding is covered by the plastic molding layer. The at least one printed circuit board and the at least one winding module are individual components.Type: ApplicationFiled: January 17, 2023Publication date: April 4, 2024Inventors: Caili Gu, Xiaoxia Yuan, Chun-Ching Yen, Yue Tsao, Huai-Pei Tung, Shaodong Zhang, Zhi-Liang Zhang
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Publication number: 20240086708Abstract: One aspect of this description relates to a convolutional neural network (CNN). The CNN includes a memory cell array including a plurality of memory cells. Each memory cell includes at least one first capacitive element of a plurality of first capacitive elements. Each memory cell is configured to multiply a weight bit and an input bit to generate a product. The at least one first capacitive element is enabled when the product satisfies a predetermined threshold. The CNN includes a reference cell array including a plurality of second capacitive elements. The CNN includes a memory controller configured to compare a first signal associated with the plurality of first capacitive elements with a second signal associated with at least one second capacitive element of the plurality of second capacitive elements, and, based on the comparison, determine whether the at least one first capacitive element is enabled.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jaw-Juinn Horng, Szu-Chun Tsao
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Publication number: 20240085934Abstract: In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.Type: ApplicationFiled: August 18, 2023Publication date: March 14, 2024Inventors: Po-Yu LAI, Szu-Chun TSAO, Jaw-Juinn HORNG
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Publication number: 20240069618Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.Type: ApplicationFiled: April 27, 2023Publication date: February 29, 2024Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
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Patent number: 11906997Abstract: A middle-range (mid) low dropout (LDO) voltage has both sinking and sourcing current capability. The mid LDO can provide a voltage reference in active mode and power mode for core only design to work in a Safe Operating Area (SOA). The output of mid LDO can track TO power and/or core power dynamically. The mid LDO can comprise a voltage reference generator and a power-down controller connected to an amplifier, which output is connected to a decoupling capacitor. The provision of a high ground signal allows the mid LDO provide the sinking and sourcing currents.Type: GrantFiled: November 30, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Szu-Chun Tsao, Yi-Wen Chen, Jaw-Juinn Horng
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Patent number: 11853880Abstract: One aspect of this description relates to a convolutional neural network (CNN). The CNN includes a memory cell array including a plurality of memory cells. Each memory cell includes at least one first capacitive element of a plurality of first capacitive elements. Each memory cell is configured to multiply a weight bit and an input bit to generate a product. The at least one first capacitive element is enabled when the product satisfies a predetermined threshold. The CNN includes a reference cell array including a plurality of second capacitive elements. The CNN includes a memory controller configured to compare a first signal associated with the plurality of first capacitive elements with a second signal associated with at least one second capacitive element of the plurality of second capacitive elements, and, based on the comparison, determine whether the at least one first capacitive element is enabled.Type: GrantFiled: August 25, 2020Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Jaw-Juinn Horng, Szu-Chun Tsao
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Publication number: 20230377661Abstract: Disclosed herein are related to a memory system including a memory cell and a circuit to operate the memory cell. In one aspect, the circuit includes a pair of transistors to electrically couple, to the bit line, a selected one of i) a voltage source to supply a reference voltage to the memory cell or ii) a sensor to sense a current through the memory cell. In one aspect, the circuit includes a first transistor. The first transistor and the bit line may be electrically coupled between the pair of transistors and the memory cell in series.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Chun Tsao, Jaw-Juinn Horng
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Publication number: 20230350442Abstract: Systems and methods as described herein may take a variety of forms. In an example, a circuit includes a first voltage stepdown module and a second voltage stepdown module. The first voltage stepdown module has a supply voltage and a first reference voltage as inputs, and an intermediate stepped down voltage as an output, the intermediate stepped down voltage being electrically coupled to a feedback input of the first voltage stepdown module. The second voltage stepdown module includes a low-dropout voltage regulator having the intermediate stepped down voltage and a second reference voltage as inputs and a target voltage as an output.Type: ApplicationFiled: June 20, 2023Publication date: November 2, 2023Inventors: Bindu Madhavi Kasina, Szu-Chun Tsao, Jaw-Juinn Horng
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Patent number: 11763891Abstract: Disclosed herein are related to a memory system including a memory cell and a circuit to operate the memory cell. In one aspect, the circuit includes a pair of transistors to electrically couple, to the bit line, a selected one of i) a voltage source to supply a reference voltage to the memory cell and ii a sensor to sense a current through the memory cell. In one aspect, the circuit includes a first transistor. The first transistor and the bit line may be electrically coupled between the pair of transistors and the memory cell in series.Type: GrantFiled: March 9, 2021Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Chun Tsao, Jaw-Juinn Horng
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Publication number: 20230266813Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor, and a controller. The battery module is configured to supply power to the electronic device. The processor has a power limit. The controller is configured to monitor a charging and discharging current of the battery module. In a power connection mode, the controller analyzes a status of the battery module and adjusts the power limit of the processor according to the charging and discharging current.Type: ApplicationFiled: October 14, 2022Publication date: August 24, 2023Applicant: ASUSTeK COMPUTER INC.Inventors: Po-Han Cheng, Chin-Chang Chang, Po-Hsin Chang, Shih-Hao Chen, Kai-Peng Chung, Ci-Syuan Wu, Chun Tsao, Teng-Chih Wang, Sheng-Yi Chen, Guan-Heng Lai
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Patent number: 11733724Abstract: In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.Type: GrantFiled: August 20, 2021Date of Patent: August 22, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yu Lai, Szu-Chun Tsao, Jaw-Juinn Horng
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Patent number: 11726510Abstract: Systems and methods as described herein may take a variety of forms. In an example, a circuit includes a first voltage stepdown module and a second voltage stepdown module. The first voltage stepdown module has a supply voltage and a first reference voltage as inputs, and an intermediate stepped down voltage as an output, the intermediate stepped down voltage being electrically coupled to a feedback input of the first voltage stepdown module. The second voltage stepdown module includes a low-dropout voltage regulator having the intermediate stepped down voltage and a second reference voltage as inputs and a target voltage as an output.Type: GrantFiled: August 27, 2021Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bindu Madhavi Kasina, Szu-Chun Tsao, Jaw-Juinn Horng
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Publication number: 20230244258Abstract: Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.Type: ApplicationFiled: April 6, 2023Publication date: August 3, 2023Inventors: Szu-Chun Tsao, Jaw-Juinn Horng, Bindu Madhavi Kasina, Yi-Wen Chen
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Patent number: 11669115Abstract: Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.Type: GrantFiled: August 27, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Chun Tsao, Jaw-Juinn Horng, Bindu Madhavi Kasina, Yi-Wen Chen
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Patent number: 11604387Abstract: A pixel structure includes a data line, a scan line, a common signal line, a first switching element, a second switching element, a first pixel electrode, and a second pixel electrode. The first switching element is electrically connected to the scan line and the data line. The second switching element is electrically connected to the scan line and the common signal line. The first pixel electrode is electrically connected to the first switching element. The second pixel electrode is electrically connected to the second switching element. The second pixel electrode surrounds the first pixel electrode.Type: GrantFiled: August 19, 2020Date of Patent: March 14, 2023Assignee: Au Optronics CorporationInventors: Yi-Chu Wang, Cheng-Wei Lai, Fu-Chun Tsao, Hsiao-Tung Lin, Wei-Cheng Cheng
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Publication number: 20230063492Abstract: Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Szu-Chun Tsao, Jaw-Juinn Horng, Bindu Madhavi Kasina, Yi-Wen Chen
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Publication number: 20230064967Abstract: Systems and methods as described herein may take a variety of forms. In an example, a circuit includes a first voltage stepdown module and a second voltage stepdown module. The first voltage stepdown module has a supply voltage and a first reference voltage as inputs, and an intermediate stepped down voltage as an output, the intermediate stepped down voltage being electrically coupled to a feedback input of the first voltage stepdown module. The second voltage stepdown module includes a low-dropout voltage regulator having the intermediate stepped down voltage and a second reference voltage as inputs and a target voltage as an output.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Bindu Madhavi Kasina, Szu-Chun Tsao, Jaw-Juinn Horng
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Publication number: 20230059336Abstract: An electrical connector assembly is applied to be disposed on a circuit board. The electrical connector assembly includes an electrical connector and a grounding metal member that is sleeved around an outer side of the electrical connector. The grounding metal member has a first surrounding segment and a second surrounding segment that outwardly extends from an end of the first surrounding segment. The second surrounding segment has a shielding portion being ring-shaped and a plurality of extension portions that extend from the shielding portion. The grounding metal member is configured to be connected to a grounding circuit of the circuit board through the shielding portion and the extension portions.Type: ApplicationFiled: July 6, 2022Publication date: February 23, 2023Inventors: PEI-SHU YEN, PING-CHUNG LO, WEI-CHUN TSAO
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Publication number: 20230053710Abstract: In some embodiments, an integrated circuit device includes multiple rows of functional cells, with each row having a cell height. At least one of rows of functional cells includes at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row. The DLVR cell includes: an input terminal, an output terminal, a voltage supply terminal, a reference voltage terminal, and one or more pairs of transistors. Each pair of transistors are arranged in cascode configuration connected between the voltage supply terminal and output terminal. The gate of one of the transistors the cascode configuration is connected to the input terminal, and the gate of the other transistor in the cascode configuration is connected to the reference voltage terminal. The four terminals each comprises a metal track in the bottom metal layer and disposed within the cell height.Type: ApplicationFiled: August 20, 2021Publication date: February 23, 2023Inventors: Po-Yu Lai, Szu-Chun Tsao, Jaw-Juinn Horng