Patents by Inventor CHUN-TSE CHEN

CHUN-TSE CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990841
    Abstract: A multi-mode hybrid control DC-DC converting circuit has a switching power converter and a microcontroller. The switching power converter has a transformer and a switching switch. The switching switch is connected to a primary-side winding of the transformer in series. The microcontroller is connected to the switching power converter and a control terminal of the switching switch. The microcontroller sets multiple thresholds according to an input voltage of the switching power converter, and determines whether a feedback voltage of the switching power converter is higher or lower than each one of the thresholds to perform a variable-frequency mode, a constant-frequency mode, or a pulse-skipping mode. The microcontroller outputs a driving signal to the switching switch and correspondingly adjusts a frequency of the driving signal according to the variable-frequency mode, the constant-frequency mode, or the pulse-skipping mode which is performed.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: May 21, 2024
    Assignee: MINMAX TECHNOLOGY CO., LTD.
    Inventors: Cheng-Chou Wu, Chun-Tse Chen
  • Publication number: 20240161818
    Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 16, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Li-Ping Huang, Yu-Fang Chen, Chun-Yen Tseng, Tzu-Feng Chang, Chun-Chieh Chang
  • Publication number: 20240164062
    Abstract: A heat dissipation device of electronic equipment has a base, a heat dissipation group, and a cover. The base has an opening, a chamber, and a boss formed in the chamber. The heat dissipation group is connected to the base and has a circuit board and a cooling blade. The circuit board is mounted in the chamber, abuts against the boss, and has a heat source area and at least one non-heat-source area. The heat source area has a first surface facing the boss and a second surface facing the opening. The cooling blade is connected to the base and is located at the second surface. The first surface and the second surface of the heat source area respectively correspond to the boss and the cooling blade in location to provide a guiding direction for heat conduction. The cover is connected to the base.
    Type: Application
    Filed: November 10, 2022
    Publication date: May 16, 2024
    Inventors: Fu Hsiang Chung, Hong Fang Chen, Chun Tse Chan
  • Patent number: 11947090
    Abstract: A lens module includes a plurality of lenses, an annular body and a reflective element. The reflective element, the lenses and the annular are sequentially arranged along an optical axis from an object side to an image side. The lenses include a first lens that is disposed closest to the object side, and a second lens that is disposed closest to the image side. The reflective element is disposed between the object side and the first lens. The annular body is disposed between the object side and the first lens, between the lenses, or between the second lens and the image side. The lens module satisfies 0.5 mm<EPA/PL<5.5 mm where EPA is an area of an entrance pupil of the lens module, and PL is a length of the reflective element.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: April 2, 2024
    Assignees: SINTAI OPTICAL (SHENZHEN) CO., LTD., ASIA OPTICAL CO., INC.
    Inventors: Chun-Yu Hsueh, Tsung-Tse Chen, Chun-Hung Huang
  • Patent number: 11943935
    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: March 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
  • Patent number: 11915755
    Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 27, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Shu-Ru Wang, Chun-Hsien Huang, Hsin-Chih Yu, Meng-Ping Chuang, Li-Ping Huang, Yu-Fang Chen
  • Publication number: 20230291317
    Abstract: A multi-mode hybrid control DC-DC converting circuit has a switching power converter and a microcontroller. The switching power converter has a transformer and a switching switch. The switching switch is connected to a primary-side winding of the transformer in series. The microcontroller is connected to the switching power converter and a control terminal of the switching switch. The microcontroller sets multiple thresholds according to an input voltage of the switching power converter, and determines whether a feedback voltage of the switching power converter is higher or lower than each one of the thresholds to perform a variable-frequency mode, a constant-frequency mode, or a pulse-skipping mode. The microcontroller outputs a driving signal to the switching switch and correspondingly adjusts a frequency of the driving signal according to the variable-frequency mode, the constant-frequency mode, or the pulse-skipping mode which is performed.
    Type: Application
    Filed: March 8, 2022
    Publication date: September 14, 2023
    Applicant: MINMAX TECHNOLOGY CO., LTD.
    Inventors: CHENG-CHOU WU, CHUN-TSE CHEN