Patents by Inventor Chun-Tsen Lu
Chun-Tsen Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250008743Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer.Type: ApplicationFiled: September 15, 2024Publication date: January 2, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
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Patent number: 12127413Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer.Type: GrantFiled: February 23, 2023Date of Patent: October 22, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
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Publication number: 20240339331Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising a medium-voltage (MV) region and a low-voltage (LV) region, forming a first gate structure and a second gate structure on the MV region and a second gate structure on the LV region, forming a patterned mask on the MV region as the patterned mask covers the first gate structure and the second gate structure and exposes the substrate between the first gate structure and the second gate structure, and then forming a first epitaxial layer between the first gate structure and the second gate structure.Type: ApplicationFiled: May 4, 2023Publication date: October 10, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chung-Fu Chang, Guang-Yu Lo, Chun-Tsen Lu
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Publication number: 20240313046Abstract: A method for fabricating a semiconductor device includes the steps of forming a fin-shaped structure on a substrate, forming a first trench and a second trench in the fin-shaped structure, forming a first dielectric layer in the first trench and the second trench, removing part of the first dielectric layer, forming a second dielectric layer in the first trench and the second trench to form a first single diffusion break (SDB) structure and a second SDB structure, and then forming a gate structure on the fin-shaped structure, the first SDB structure, and the second SDB structure.Type: ApplicationFiled: April 13, 2023Publication date: September 19, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Guang-Yu Lo, Chun-Tsen Lu, Chung-Fu Chang, Chih-Shan Wu, Yu-Hsiang Lin, Wei-Hao Chang
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Publication number: 20240282843Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.Type: ApplicationFiled: May 2, 2024Publication date: August 22, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chung-Fu Chang, Kuan-Hung Chen, Guang-Yu Lo, Chun-Chia Chen, Chun-Tsen Lu
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Patent number: 12009409Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.Type: GrantFiled: March 6, 2023Date of Patent: June 11, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Fu Chang, Kuan-Hung Chen, Guang-Yu Lo, Chun-Chia Chen, Chun-Tsen Lu
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Publication number: 20230207668Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chung-Fu Chang, Kuan-Hung Chen, Guang-Yu Lo, Chun-Chia Chen, Chun-Tsen Lu
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Publication number: 20230207669Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.Type: ApplicationFiled: March 7, 2023Publication date: June 29, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chung-Fu Chang, Kuan-Hung Chen, Guang-Yu Lo, Chun-Chia Chen, Chun-Tsen Lu
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Publication number: 20230200088Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer.Type: ApplicationFiled: February 23, 2023Publication date: June 22, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
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Patent number: 11631753Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.Type: GrantFiled: February 22, 2019Date of Patent: April 18, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Fu Chang, Kuan-Hung Chen, Guang-Yu Lo, Chun-Chia Chen, Chun-Tsen Lu
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Patent number: 11621296Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.Type: GrantFiled: April 6, 2021Date of Patent: April 4, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
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Patent number: 11145733Abstract: The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.Type: GrantFiled: September 27, 2020Date of Patent: October 12, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chin-Hung Chen, Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Yu-Hsiang Lin, Po-Wen Su, Chung-Fu Chang, Guang-Yu Lo, Chun-Tsen Lu
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Publication number: 20210225932Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.Type: ApplicationFiled: April 6, 2021Publication date: July 22, 2021Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
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Patent number: 11004897Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.Type: GrantFiled: August 4, 2019Date of Patent: May 11, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
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Publication number: 20210005662Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.Type: ApplicationFiled: August 4, 2019Publication date: January 7, 2021Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
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Publication number: 20200235227Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.Type: ApplicationFiled: February 22, 2019Publication date: July 23, 2020Inventors: Chung-Fu Chang, Kuan-Hung Chen, Guang-Yu Lo, Chun-Chia Chen, Chun-Tsen Lu
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Patent number: 10475744Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, an isolation structure, an outer structure, and a gate structure. The isolation structure is disposed on the substrate. The outer structure surrounds a sidewall of the isolation structure. The gate structure surrounds a central part of the outer structure, so that the central part covered by the gate structure becomes a channel region, and the outer structure at both sides of the central part respectively becomes a source region and a drain region.Type: GrantFiled: October 6, 2017Date of Patent: November 12, 2019Assignee: United Microelectronics Corp.Inventors: Kuan-Hung Chen, Rung-Yuan Lee, Chun-Tsen Lu
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Patent number: 10446448Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; a first oxide layer on the first fin-shaped structure; a second oxide layer on and directly contacting the first oxide layer and the STI; and a third oxide layer on the second fin-shaped structure, wherein a thickness of the third oxide layer is less than a thickness of the first oxide layer.Type: GrantFiled: October 30, 2018Date of Patent: October 15, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hao Lin, Hsin-Yu Chen, Chun-Tsen Lu, Shou-Wei Hsieh
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Patent number: 10403715Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor nanowire, a gate structure, a first metal nanowire and a second metal nanowire. The semiconductor nanowire is disposed vertically on the substrate. The gate structure surrounds a middle portion of the semiconductor nanowire. The first metal nanowire is located on a side of the semiconductor nanowire and is electronically connected to a lower portion of the semiconductor nanowire. The second metal nanowire is located on the other side of the semiconductor nanowire and is electronically connected to the gate structure.Type: GrantFiled: December 17, 2018Date of Patent: September 3, 2019Assignee: United Microelectronics Corp.Inventors: Rung-Yuan Lee, Chun-Tsen Lu, Kuan-Hung Chen
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Patent number: 10290723Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.Type: GrantFiled: May 17, 2018Date of Patent: May 14, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang