Patents by Inventor Chun-Wei Liao
Chun-Wei Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240114683Abstract: A method of manufacturing a memory device includes providing a substrate and sequentially forming a stack layer and a hard mask layer on the substrate. The method includes forming a first patterned mandrel and a plurality of second patterned mandrels on the hard mask layer, wherein the first patterned mandrel is adjacent to and spaced apart from an end of the second patterned mandrels in the first direction. The method further includes using the first patterned mandrel and the second patterned mandrels as masks, patterning the hard mask layer and the stack layer sequentially to form a dummy structure and a plurality of word lines separated from each other on the substrate. A portion of the stack layer corresponding to the first mandrel is formed into the dummy structure, and a portion of the stack layer corresponding to the second patterned mandrels is formed into the word lines.Type: ApplicationFiled: October 3, 2022Publication date: April 4, 2024Inventors: Tsung-Wei LIN, Kun-Che WU, Chun-Yen LIAO, Chun-Sheng WU
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Patent number: 11946802Abstract: An ambient light sensor includes a substrate, a metasurface disposed on the substrate, and an aperture layer disposed on the substrate. The metasurface includes a plurality of nanostructures and a filling layer laterally surrounding the plurality of nanostructures. The aperture layer laterally separates the metasurface into a plurality of sub-meta groups.Type: GrantFiled: March 29, 2023Date of Patent: April 2, 2024Assignee: VISERA TECHNOLOGIES COMPANY LIMITEDInventors: Shih-Liang Ku, Zi-Han Liao, Chun-Wei Huang
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Publication number: 20240087951Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Chun-Hao Kung, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
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Publication number: 20240079758Abstract: An electronic device includes a metal back cover, a metal frame, and a first, second, third, and fourth radiators. The metal frame includes a discrete part and two connection parts. The connection parts are located by two sides of the discrete part, separated from the discrete part, and connected to the metal back cover. A U-shaped slot is formed between the discrete part and the metal back cover and between the discrete part and the connection parts. The first radiator is separated from the discrete part and includes a feed end. The second, third, and fourth radiators are connected to the discrete part and the metal back cover. The third radiator is located between the first and second radiators. The first radiator is located between the third and fourth radiators. The discrete part and the first, second, third, and fourth radiators form an antenna module together.Type: ApplicationFiled: August 2, 2023Publication date: March 7, 2024Applicant: PEGATRON CORPORATIONInventors: Chien-Yi Wu, Chao-Hsu Wu, Chih-Wei Liao, Hau Yuen Tan, Shih-Keng Huang, Wen-Hgin Chuang, Lin-Hsu Chiang, Chang-Hua Wu, Han-Wei Wang, Chun-Jung Hu
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Publication number: 20230389294Abstract: A transistor includes: a substrate including an active area; a gate structure penetrating through the active area and including a gate and a gate dielectric layer, in which the gate dielectric layer covers sidewalls and a bottom of the gate; a channel layer located on a side of the gate dielectric layer away from the gate, in which the channel layer includes a metal oxide semiconductor layer, in which the active area includes a first active layer and a second active layer located at two sides of the gate structure, and the first active layer and the second active layer are in contact with the channel layer.Type: ApplicationFiled: January 7, 2023Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: CHUN-WEI LIAO, Xiaoguang WANG, Deyuan XIAO, TZUNG-HAN LEE
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Publication number: 20230386837Abstract: A system for manufacturing a semiconductor device comprises an edge coating device. The edge coating device comprises a first stage, a first shielding disk, one or more first openings, one or more second openings, and a resist dispensing module.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Chun-Wei LIAO, Tung-Hung FENG, Hui-Chun LEE
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Patent number: 11798800Abstract: A solvent recycle system minimizes chemical consumption used in various semiconductor processes. The solvent is recycled from a nozzle bath via the addition of buffer tank to connect the bath and circulation pumps. Improvements to the bath design further maintain solvent cleanness by preventing intrusion of particles and overflow conditions in the bath.Type: GrantFiled: June 25, 2021Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Wei Liao, Tung-Hung Feng, Hui-Chun Lee, Shih-Che Wang
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Publication number: 20230108126Abstract: A method for manufacturing a semiconductor device includes forming a forming a photoresist layer over a semiconductor substrate and selectively exposing the photoresist layer to actinic radiation. After selectively exposing the photoresist layer to actinic radiation, storing the semiconductor substrate in a semiconductor substrate container under an ambient of extreme dry clean air or inert gas. The method also includes after the storing the semiconductor substrate, performing a first heating of the photoresist layer.Type: ApplicationFiled: August 8, 2022Publication date: April 6, 2023Inventors: Chun-Wei LIAO, Sheng-Wen JIANG, Jan-Liang YANG, Hui-Chun LEE
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Publication number: 20230063235Abstract: In a method of manufacturing a semiconductor device, a hydrophobic solvent as a gas is directed to flow over a bevel region of a wafer. A layer of the hydrophobic solvent is deposited on an upper bevel of the bevel region on top surface of the wafer and on a lower bevel of the bevel region on bottom surface of the wafer. A metal-containing photo resist layer is disposed on an internal region of the top surface of the wafer enclosed by the bevel region. During a subsequent processing operation, a photo resist material of the metal-containing photo resist layer is blocked off inside the top surface of the wafer by the layer of the hydrophobic solvent.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Chun-Wei LIAO, Tung-Hung FENG, Hui-Chun LEE
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Publication number: 20230043243Abstract: A method of operating a wet process apparatus, includes dispensing a solution from a nozzle and directing the solution to a bath through an inlet port. A purge gas is injected into the bath to force flow of the solution from the bath to a buffer tank. A condition of the fluid within the buffer tank is monitored with a sensor. The solution is circulated to a pump and then through a filter before returning the solution to the nozzle. Overflow solution is directed out of the bath via an overflow path to a drain for preventing an overflow condition.Type: ApplicationFiled: October 17, 2022Publication date: February 9, 2023Inventors: Chun-Wei LIAO, Tung-Hung FENG, Hui-Chun LEE, Shih-Che WANG
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Publication number: 20230010749Abstract: A solution dispense system for a semiconductor manufacturing process includes a longer circulation loop in order to minimize the idle section from resist pump to dispense nozzle. A t-valve and control valve are disposed close to the nozzle in order to decrease the idle section and reduce material consumption.Type: ApplicationFiled: July 9, 2021Publication date: January 12, 2023Inventors: Chun-Wei LIAO, Tung-Hung FENG, Hui-Chun LEE, Shih-Che WANG
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Publication number: 20220415646Abstract: A solvent recycle system minimizes chemical consumption used in various semiconductor processes. The solvent is recycled from a nozzle bath via the addition of buffer tank to connect the bath and circulation pumps. Improvements to the bath design further maintain solvent cleanness by preventing intrusion of particles and overflow conditions in the bath.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Inventors: Chun-Wei LIAO, Tung-Hung FENG, Hui-Chun LEE, Shih-Che WANG
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Publication number: 20220405140Abstract: A security system is disclosed. The security system includes a memory and a processor. The memory is configured to store several applications, in which several applications include several relationships. The processor is coupled to the memory, in which the processor is configured to manage several applications according to several relationships and at least one of a time driven method and an event driven method, in which the several relationships include a parent-child relationship, a function-group relationship, and an app-type relationship, to receive several input signals from several sources, and to display a screen picture of the several input signals according to several drawing parameters, and when several applications are running, the processor is further configured to allocate several resources of the security system to several applications according to several weighting values.Type: ApplicationFiled: June 17, 2022Publication date: December 22, 2022Inventors: Kai-Shian MOOI, Chun-Wei LIAO
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Publication number: 20220405139Abstract: A virtual hardware management device is provided, which includes a memory and a processing unit. The processing unit is configured for executing the multiple instructions to perform the following operations: when detecting that the load rate is more than the high level threshold, comparing respective priorities of multiple processing flows; selecting at least one of the multiple processing flows to perform at least one of analysis frequency reduction processing, detection reduction processing, or flow pause processing according to a comparing result until the load rate is not more than the high level threshold; and generating respective resource allocation ratio of multiple operators in the multiple processing flows according to respective resource weights of the multiple operators, and using a virtual hardware unit to execute the multiple operators according to the multiple resource allocation ratios.Type: ApplicationFiled: June 17, 2022Publication date: December 22, 2022Inventors: Kai-Shian MOOI, Chun-Wei LIAO
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Patent number: 11532559Abstract: A semiconductor device includes a first dielectric layer, a cobalt-containing conductive feature, a non-cobalt conductive feature, a second dielectric layer, a first tungsten contact feature, a second tungsten contact feature, and a tungsten barrier layer. The cobalt-containing conductive feature is disposed in the first dielectric layer. The non-cobalt conductive feature is disposed in the first dielectric layer, and is spaced apart from the cobalt-containing conductive feature. The second dielectric layer is disposed over the first dielectric layer. The first tungsten contact feature is disposed in the second dielectric layer, and is electrically connected to the cobalt-containing conductive feature. The second tungsten contact feature is disposed in the second dielectric layer, and is electrically connected to the non-cobalt conductive feature.Type: GrantFiled: February 25, 2021Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Jhen Liao, Huei-Shan Wu, Chun-Wei Liao, Yi-Lii Huang
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Publication number: 20220293587Abstract: The present disclosure in various embodiments provides a hardened resist layer that can reduce resist scum defects in a resist layer. In one embodiment, a lithography method is provided. The method includes forming a resist layer over a substrate, performing an exposure process on the resist layer, performing a developing process on the resist layer to form a patterned resist layer having a plurality resist segments, exposing the patterned resist layer to a vacuum ultraviolet (VUV) radiation, and subjecting the resist pattern a de-scum process.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Wei LIAO, Hui-Chun LEE
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Publication number: 20220270980Abstract: A semiconductor device includes a first dielectric layer, a cobalt-containing conductive feature, a non-cobalt conductive feature, a second dielectric layer, a first tungsten contact feature, a second tungsten contact feature, and a tungsten barrier layer. The cobalt-containing conductive feature is disposed in the first dielectric layer. The non-cobalt conductive feature is disposed in the first dielectric layer, and is spaced apart from the cobalt-containing conductive feature. The second dielectric layer is disposed over the first dielectric layer. The first tungsten contact feature is disposed in the second dielectric layer, and is electrically connected to the cobalt-containing conductive feature. The second tungsten contact feature is disposed in the second dielectric layer, and is electrically connected to the non-cobalt conductive feature.Type: ApplicationFiled: February 25, 2021Publication date: August 25, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Jhen LIAO, Huei-Shan WU, Chun-Wei LIAO, Yi-Lii HUANG
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Publication number: 20200174374Abstract: A method for manufacturing a semiconductor device includes forming a forming a photoresist layer over a semiconductor substrate and selectively exposing the photoresist layer to actinic radiation. After selectively exposing the photoresist layer to actinic radiation, storing the semiconductor substrate in a semiconductor substrate container under an ambient of extreme dry clean air or inert gas. The method also includes after the storing the semiconductor substrate, performing a first heating of the photoresist layer.Type: ApplicationFiled: November 26, 2019Publication date: June 4, 2020Inventors: Chun-Wei LIAO, Sheng-Wen Jiang, Jan-Liang YANG, Hui-Chun LEE
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Patent number: 8412007Abstract: The present invention relates to a 3-D waveguide coupling device capable of two-step coupling and a manufacture method thereof, the 3-D waveguide coupling device comprises: a first substrate, at least one waveguide layer, at least one assisting grating, at least one coupling material layer, and at least one 3-D tapered structure layer, wherein 3-D waveguide coupling device is able to couple the light into the waveguide layer by way of two-step coupling through the 3-D tapered structure layer, the coupling material layer and the assisting grating. Moreover, the light can also be coupled out from the waveguide layer through the assisting grating, the coupling layer, and the 3-D tapered structure. The manufacture method is adapted to fabricate the 3-D waveguide coupling device capable of two-step coupling via the present semiconductor process technology without increasing any other new equipment.Type: GrantFiled: May 27, 2010Date of Patent: April 2, 2013Assignee: National Tsing Hua UniversityInventors: Ming-Chang Lee, Yao-Tsu Yang, Chun-Wei Liao, Sheng-Wen Huang
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Patent number: 8347896Abstract: An artificial eyelash structure includes a mounting member having a bonding portion for adhering to an eyelid and a bendable portion for enabling the bonding portion to be curved into a smoothly arched shape when bending the bonding portion upwards or downwards, and multiple eyelashes connected with the mounting member. The artificial eyelash structure is prepared by: forming a mounting member from a thin film, and then processing the thin film of the mounting member into a bonding portion and a bendable portion such that the bendable portion enables the bonding portion to be bent upwards or downwards, and then connecting eyelashes with the mounting member.Type: GrantFiled: May 10, 2010Date of Patent: January 8, 2013Inventor: Chun-Wei Liao