Patents by Inventor Chun Wei Lin
Chun Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250098238Abstract: A semiconductor device includes a first fin-shaped structure and a second fin-shaped structure on a substrate, a bump between the first fin-shaped structure and the second fin-shaped structure, a first recess between the first fin-shaped structure and the bump, and a second recess between the second fin-shaped structure and the bump. Preferably, a top surface of the bump includes a curve concave upward, a width of the bump is greater than twice the width of the first fin-shaped structure, and a height of the bump is less than one fourth of the height of the first fin-shaped structure.Type: ApplicationFiled: October 23, 2023Publication date: March 20, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ting Chiang, Tien-Shan Hsu, Po-Chang Lin, Lung-En Kuo, Hao-Che Feng, Ping-Wei Huang
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Patent number: 12249649Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.Type: GrantFiled: March 22, 2021Date of Patent: March 11, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
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Publication number: 20250081632Abstract: A solar cell module includes a first substrate, a second substrate, at least one cell unit, a first packaging film, a second packaging film, a first protective layer, a second protective layer, and a plurality of support members. The first substrate and the second substrate are disposed opposite to each other. The cell unit is disposed between the first substrate and the second substrate. The first packaging film is disposed between the cell unit and the first substrate. The second packaging film is disposed between the cell unit and the second substrate. The first protective layer is disposed between the cell unit and the first packaging film. The second protective layer is disposed between the cell unit and the second packaging film. The support members are respectively disposed between the first packaging film and the second packaging film and surround at least two opposite sides of the cell unit.Type: ApplicationFiled: August 29, 2024Publication date: March 6, 2025Applicant: Industrial Technology Research InstituteInventors: Hsin-Chung Wu, Chun-Wei Su, Tzu-Ting Lin, En-Yu Pan, Yu-Tsung Chiu, Chih-Lung Lin, Teng-Yu Wang, Chiou-Chu Lai, Ying-Jung Chiang
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Publication number: 20250073451Abstract: An in vitro training method for training genioglossus muscle strength includes adhering an electrode patch of an in vitro training device to a bottom of a chin of a user during a non-sleep period. The electrode patch receives an electrical stimulation signal from an electrical stimulation module of the in vitro training device to stimulate the genioglossus muscle of the user through transdermal electrical stimulation. The electrode patch includes a body surface adhering face and an assembling face opposite to the body surface adhering face. The body surface adhering face is adhered to the bottom of the chin of the user to align with the genioglossus muscle. The electrical stimulation module is disposed on the assembling face and in electrical connection with the electrode patch. The electrical stimulation module sends an electrical stimulation signal to stimulate the genioglossus muscle through transdermal electrical stimulation.Type: ApplicationFiled: August 28, 2023Publication date: March 6, 2025Inventors: Bol-Wei Huang, Yu-Sheng Lin, Tung-Lin Tsai, Chun-Chieh Tseng
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Patent number: 12242321Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.Type: GrantFiled: April 27, 2023Date of Patent: March 4, 2025Assignee: ASUSTEK COMPUTER INC.Inventors: Wen Che Chung, Hui Chuan Lo, Hao-Hsuan Lin, Chun Tsao, Jun-Fu Chen, Ming-Hung Yao, Jia-Wei Zhang, Kuan-Lun Chen, Ting-Chao Lin, Cheng-Yen Lin, Chunyen Lai
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Publication number: 20250065110Abstract: An in vitro training method includes scanning a user's oral cavity to create a first oral cavity model. An articulator body is selected according to the first oral cavity model, and plural first customized electrode sheets are formed and assembled onto the articulator body to obtain an in vitro training device. The user bites the in vitro training device during a non-sleep period and uses the plural first customized electrode sheets to proceed with electrical stimulation on a top surface and two sides of a tongue of the user, thereby training a muscular endurance of infrahyoid muscles of the user for a training period. The user's oral cavity is scanned again to create a second oral cavity model. The first oral cavity model is compared with the second oral cavity model to timely renew the customized electrode sheets when the image over rate is lower than 80%.Type: ApplicationFiled: August 24, 2023Publication date: February 27, 2025Inventors: BOL-WEI HUANG, YU-SHENG LIN, TUNG-LIN TSAI, CHUN-CHIEH TSENG
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Publication number: 20250066899Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.Type: ApplicationFiled: August 23, 2023Publication date: February 27, 2025Inventors: Chun-Yen LIAO, I. LEE, Shu-Lan CHANG, Sheng-Hsuan LIN, Feng-Yu CHANG, Wei-Jung LIN, Chun-I TSAI, Chih-Chien CHI, Ming-Hsing TSAI, Pei Shan CHANG, Chih-Wei CHANG
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Publication number: 20250072294Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.Type: ApplicationFiled: November 14, 2024Publication date: February 27, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Wei Liu, Jia-Feng Fang, Chun-Hsien Lin
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Patent number: 12237395Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.Type: GrantFiled: February 20, 2022Date of Patent: February 25, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ko-Wei Lin, Chun-Chieh Chiu, Chun-Ling Lin, Shu Min Huang, Hsin-Fu Huang
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Patent number: 12237218Abstract: A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.Type: GrantFiled: May 6, 2022Date of Patent: February 25, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chang-Ting Chung, Shih-Wei Yeh, Kai-Chieh Yang, Yu-Ting Wen, Yu-Chen Ko, Ya-Yi Cheng, Min-Hsiu Hung, Chun-Hsien Huang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Patent number: 12237329Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.Type: GrantFiled: December 1, 2023Date of Patent: February 25, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
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Patent number: 12237400Abstract: A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.Type: GrantFiled: April 6, 2022Date of Patent: February 25, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chieh-Wei Chen, Jian-Jou Lian, Tzu-Ang Chiang, Po-Yuan Wang, Yu-Shih Wang, Chun-Neng Lin, Ming-Hsi Yeh
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Publication number: 20250062202Abstract: A semiconductor die and methods of forming the same and a package structure are provided. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads over the semiconductor substrate, a passivation layer over the semiconductor substrate and partially covering the plurality of conductive pads, an interconnecting line disposed on the passivation layer, and a plurality of connectors disposed on and electrically connected to the plurality of conductive pads. Each of the plurality of connectors includes a stacked structure of a first conductive pillar and a second conductive pillar disposed directly on the first conductive pillar, wherein a span of the second conductive pillar is smaller than a span of the first conductive pillar, and an orthogonal projection of the second conductive pillar falls within an orthogonal projection of the first conductive pillar, and the interconnecting line is located beside and spaced apart from the plurality of connectors.Type: ApplicationFiled: August 17, 2023Publication date: February 20, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Yi Sung, Ta-Hsuan Lin, Hua-Wei Tseng, Mill-Jer Wang
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Publication number: 20250063776Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a first electrically conductive structure. The semiconductor substrate has a planar device region and a fin device region. The semiconductor substrate includes a mesa structure disposed in the planar device region and fin-shaped structures disposed in the fin device region. The isolation structure is disposed on the semiconductor substrate and includes a first portion which is disposed on the planar device region and covers a sidewall of the mesa structure, and the isolation structure further includes a second portion which is disposed on the fin device region and located between the fin-shaped structures. The first electrically conductive structure is disposed on the planar device region. The first electrically conductive structure is partly disposed above the mesa structure in a vertical direction and partly disposed above the first portion of the isolation structure in the vertical direction.Type: ApplicationFiled: September 27, 2023Publication date: February 20, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Yu Chen, Chun-Hao Lin, Yuan-Ting Chuang, Shou-Wei Hsieh
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Patent number: 12230595Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.Type: GrantFiled: May 28, 2021Date of Patent: February 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Da Cheng, Yung-Ching Chao, Chun Kai Tzeng, Cheng Jen Lin, Chin Wei Kang, Yu-Feng Chen, Mirng-Ji Lii
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Patent number: 12227983Abstract: An automatic vehicle-door activating sensing system and a method therefor are provided. The system includes: a distance sensing antenna module and an activating antenna module for generating signals; a processor generates a first distance information, a second distance information, and a activating information according to the signals. When the first distance information is less than a distance threshold and a waveform of the activating information changes, the processor generates and transmits a ready-to-activate signal to an in-vehicle system. When the second distance information is greater than the distance threshold, the processor generates and transmits a vehicle door activating signal to the in-vehicle system. The in-vehicle system can activate the vehicle door after receiving the signals in sequence. With one radar, the invention can automatically activate the vehicle door based on a user's position and kicking behavior, thereby preventing misoperation caused by detection.Type: GrantFiled: October 24, 2022Date of Patent: February 18, 2025Assignee: RoyalTek Company Ltd.Inventors: Kuo Wei Lin, Chun Yen Chen
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Patent number: 12230572Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.Type: GrantFiled: May 18, 2023Date of Patent: February 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Yi-Hsun Chiu, Yi-Bo Liao, Kuan-Lun Cheng, Wei-Cheng Lin, Wei-An Lai, Ming Chian Tsai, Jiann-Tyng Tzeng, Hou-Yu Chen, Chun-Yuan Chen, Huan-Chieh Su
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Publication number: 20250054900Abstract: A package structure includes a circuit substrate, a package unit, a thermal interface material and a cover. The package unit is disposed on and electrically connected with the circuit substrate. The package unit includes a first surface facing the circuit substrate and a second surface opposite to the first surface. A underfill is disposed between the package unit and the circuit substrate, surrounding the package unit and partially covering sidewalls of the package unit. The cover is disposed over the package unit and over the circuit substrate. An adhesive is disposed on the circuit substrate and between the cover and the circuit substrate. The thermal interface material includes a metal-type thermal interface material and is disposed between the cover and the package unit. The thermal interface material physically contacts the second surface and the sidewalls of the package unit and physically contacts the underfill.Type: ApplicationFiled: August 7, 2023Publication date: February 13, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Yen Lan, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Ying-Ching Shih, Yu-Wei Lin
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Patent number: D1062545Type: GrantFiled: May 7, 2023Date of Patent: February 18, 2025Assignees: Acer Incorporated, Acer Gadget Inc.Inventors: Yun Cheng, Ker-Wei Lin, Hao-Ming Chang, Chun-Ta Chen, Wei-Chen Lee, Chih-Yuan Chang
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Patent number: D1063712Type: GrantFiled: May 7, 2023Date of Patent: February 25, 2025Assignees: Acer Incorporated, Acer Gadget Inc.Inventors: Yun Cheng, Ker-Wei Lin, Hao-Ming Chang, Chun-Ta Chen, Wei-Chen Lee, Chih-Yuan Chang