Abstract: An immersion cooling device includes a housing defining a chamber, a working liquid received in the chamber, a condenser received in the chamber and located outside the working liquid, and at least one support plate received in the chamber. Each of the at least one support plate includes a first portion and a second portion connected to the first portion. The first portion is immersed in the working liquid and configured to hold an electronic device. The second portion protrudes from the working liquid. The second portion defines a slot extending through the second portion, and an opening of the slot faces the condenser.

Abstract: An electronic apparatus includes at least one heat generating component and an immersion cooling system. The immersion cooling system includes a main tank and a liquid amount adjusting module. The main tank is adapted to contain a heat dissipation medium, and the heat generating component is disposed in the main tank to be immersed in the heat dissipation medium. The liquid adjusting module includes an auxiliary tank and a pump. The auxiliary tank is adjacent to the main tank, and the heat dissipation medium in the main tank is adapted to be overflowed into the auxiliary tank. The pump is disposed in the auxiliary tank and adapted to drive the heat dissipation medium in the auxiliary tank to flow into the main tank.

Abstract: A semiconductor structure includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a second conductive layer arranged within the dielectric layer and electrically connected to the first conductive layer, the second conductive layer including a sidewall distant from the dielectric layer by a width; and a first blocking layer over a surface of the first conductive layer between the second conducive layer and the dielectric layer. The first blocking layer includes at least one element of a precipitant.

Abstract: A storage environment monitoring device is capable of measuring and/or monitoring various parameters of an environment inside a storage area, such as airflow, temperature, and humidity, to increase the storage quality of semiconductor components stored in the storage area. The storage environment monitoring device is capable of measuring and/or monitoring the parameters of the environment inside the storage area without having to open an enclosure that is storing the semiconductor components in the storage area. This reduces exposure of the semiconductor components to contamination and other environmental factors.

Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

Abstract: A backlight module includes a film, a light guide plate disposed under the film, and a circuit board disposed under the light guide plate and provided with a light-emitting unit. The film includes a single-key transparent area, a light-shielding area disposed around the single-key transparent area, and a side transparent area disposed adjacent to or along an edge of the film. The light guide plate has a first microstructure group and a through hole correspondingly disposed under the single-key transparent area, a second microstructure group correspondingly disposed under the side transparent area, and a light-transmitting area partially correspondingly disposed under the light-shielding area. The light-emitting unit is accommodated in the through hole. A number of microstructures or a light-emitting area of the second microstructure group is greater than a number of microstructures or a light emitting area of the first microstructure group.

Abstract: An electronic device includes a memory usage identification circuit and a system-level cache (SLC). The memory usage identification circuit obtains a memory usage indicator that depends on memory usage of a storage space allocated in a system memory at which memory access is requested by a physical address. The SLC includes a cache memory and a cache controller. The cache controller performs cache management upon the cache memory according to the physical address and the memory usage indicator.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Abstract: A connector assembly comprises a wire end connector, a board end connector, and an operating element. The board end connector includes a base and an extending tube body, which laterally forms a protrusion. The wire end connector includes a body and a wire connecting portion. The body has a shell that forms a guide groove and a side hole. The operating element has a pivot portion, a first extending arm, and a second extending arm. When the board end connector and the wire end connector are in an initial state and the operating element is in an unlocked position, the second extending arm is away from the guide groove. When the board end connector and the wire end connector are switched to a mating state, the protrusion contacts the first extending arm, causing the operating element to rotate from the unlocked position to a locked position.

Abstract: A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.

Abstract: A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.

Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Abstract: An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.

Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

Abstract: Some implementations described herein include techniques and apparatus for forming a semiconductor device including a semiconductor resistor structure. The semiconductor resistor structure (e.g., a low-impedance thin-film resistor structure) may include a resistive layer having an approximately rectangular shape (e.g., a width-to-length ratio that is less than approximately one). The semiconductor resistor structure includes contact structures connected to the resistive layer, a conductive bus structure having an approximately rectangular shape that connects to the contact structures, and an electrical terminal (e.g., a routing pin) centrally located at or near an edge of the conductive bus structure.

Abstract: A semiconductor device includes a gate structure on a substrate, a single diffusion break (SDB) structure adjacent to the gate structure, a first spacer adjacent to the gate structure, a second spacer adjacent to the SDB structure, a source/drain region between the first spacer and the second spacer, an interlayer dielectric (ILD) layer around the gate structure and the SDB structure, and a contact plug in the ILD layer and on the source/drain region. Preferably, a top surface of the second spacer is lower than a top surface of the first spacer.

Abstract: An operation power source for an operation power source supplying power to a synchronous rectifier controller is charged according to the invention. The synchronous rectifier controller controls a synchronous rectifier in response to a channel signal of the synchronous rectifier, generating SR ON times and SR OFF times. It is determined whether the channel signal resonates in a first SR OFF time, to provide an oscillation record accordingly. In a second SR OFF time after the first SR OFF time, in response to the oscillation record, a portion of resonance energy that causes the channel signal resonating is directed to charge the operation power source.

Abstract: An electronic apparatus includes at least one heat generating component and an immersion cooling system. The immersion cooling system includes a main tank and a liquid amount adjusting module. The main tank is adapted to contain a heat dissipation medium, and the heat generating component is disposed in the main tank to be immersed in the heat dissipation medium. The liquid adjusting module includes an auxiliary tank and a pump. The auxiliary tank is adjacent to the main tank, and the heat dissipation medium in the main tank is adapted to be overflowed into the auxiliary tank. The pump is disposed in the auxiliary tank and adapted to drive the heat dissipation medium in the auxiliary tank to flow into the main tank.