Patents by Inventor Chun-Wei Yu
Chun-Wei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250089334Abstract: A semiconductor includes a substrate. A gate structure is disposed on the substrate. A liner oxide contacts a side of the gate structure. A silicon oxide spacer contacts the liner oxide. An end of the silicon oxide spacer forms a kink profile. A silicon nitride spacer contacts the silicon oxide spacer and a tail of the silicon nitride spacer covers part of the kink profile. A stressor covers the silicon nitride spacer and the substrate.Type: ApplicationFiled: October 13, 2023Publication date: March 13, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Fan Li, Chen-Ming Wang, Po-Ching Su, Pei-Hsun Kao, Ti-Bin Chen, Chun-Wei Yu, Chih-Chiang Wu
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Publication number: 20250072060Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.Type: ApplicationFiled: November 11, 2024Publication date: February 27, 2025Applicant: United Microelectronics Corp.Inventors: Kuang-Hsiu Chen, Wei-Chung Sun, Chao Nan Chen, Chun-Wei Yu, Kuan Hsuan Ku, Shao-Wei Wang
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Patent number: 11999968Abstract: This disclosure provides modified T cells possessing both cell killing function and antigen presenting cell function and method of culturing the same. By administration of the modified T cell, cancer cells in a subject may be effectively inhibited via cell-mediated immunity.Type: GrantFiled: October 22, 2021Date of Patent: June 4, 2024Assignee: FullHope Biomedical Co., LtdInventors: Jan-Mou Lee, Chun-Wei Yu, Chih-Hao Fang, Ya-Fang Cheng, Li-Tzong Chen
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Publication number: 20230369460Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.Type: ApplicationFiled: June 9, 2022Publication date: November 16, 2023Applicant: United Microelectronics Corp.Inventors: Kuang-Hsiu Chen, Wei-Chung Sun, Chao Nan Chen, Chun-Wei Yu, Kuan Hsuan Ku, Shao-Wei Wang
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Publication number: 20230352587Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.Type: ApplicationFiled: July 4, 2023Publication date: November 2, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Chun-Wei Yu, Yu-Ren Wang
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Patent number: 11735661Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.Type: GrantFiled: May 26, 2021Date of Patent: August 22, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Chun-Wei Yu, Yu-Ren Wang
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Publication number: 20230131917Abstract: This disclosure provides modified T cells possessing both cell killing function and antigen presenting cell function and method of culturing the same. By administration of the modified T cell, cancer cells in a subject may be effectively inhibited0 via cell-mediated immunity.Type: ApplicationFiled: October 22, 2021Publication date: April 27, 2023Inventors: JAN-MOU LEE, CHUN-WEI YU, CHIH-HAO FANG, YA-FANG CHENG
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Publication number: 20210280717Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.Type: ApplicationFiled: May 26, 2021Publication date: September 9, 2021Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Chun-Wei Yu, Yu-Ren Wang
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Publication number: 20210248603Abstract: A block chain-based transaction processing method and apparatus are disclosed, in which an intermediate computing device receives and validates a first block record from, and generates and sends a second block record to, a first computing device; receives a third block record generated by a second computing device after validating the second block record from the intermediate computing device; generates and sends a fourth block record to the second computing device after validating the third block record, receives from the first computing device a fifth block record generated by the first computing device after validating the fourth block record from the intermediate computing device; receives from the second computing device a sixth block record generated by the second computing device after validating the fifth block record from the intermediate computing device; and broadcasts the first to sixth block records to other computing devices after validating the fifth and sixth block records.Type: ApplicationFiled: April 26, 2021Publication date: August 12, 2021Inventors: Ching Song WU, Chun-Wei YU, Chih Sheng WANG, Yi Hung LIANG, Cheng-Ying WU
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Patent number: 11049971Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.Type: GrantFiled: November 30, 2018Date of Patent: June 29, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Chun-Wei Yu, Yu-Ren Wang
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Patent number: 10796943Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned mask layer is formed on a semiconductor substrate. An isolation trench is formed in the semiconductor substrate by removing a part of the semiconductor substrate. A liner layer is conformally formed on an inner sidewall of the isolation trench. An implantation process is performed to the liner layer. The implantation process includes a noble gas implantation process. An isolation structure is at least partially formed in the isolation trench after the implantation process. An etching process is performed to remove the patterned mask layer after forming the isolation structure and expose a top surface of the semiconductor substrate. A part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process. The implantation process is configured to modify the etch rate of the liner layer in the etching process.Type: GrantFiled: November 6, 2018Date of Patent: October 6, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Shi-You Liu, Shao-Hua Hsu
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Publication number: 20200250665Abstract: A blockchain-based electronic transaction system free of sales platform comprises a computing device. The blockchain includes a customer endpoint and a vendor endpoint, the customer endpoint and the vendor endpoint corresponding to a customer device and a vendor device, respectively. The computing device comprises a data storage module and a procurement management module. The data storage module stores at least one product sales channel public key and at least one product data. The customer device is connected to the computing device through the blockchain by a product public key of a product sales channel, and acquires the product data from the data storage module. The procurement management module is configured to enable the customer device to establish a product order message with the vendor endpoint, and to broadcast the message in the blockchain. The product order message is encrypted and authenticated by a customer private key.Type: ApplicationFiled: October 2, 2018Publication date: August 6, 2020Inventors: Ching Song WU, Chun-Wei YU
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Patent number: 10700202Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.Type: GrantFiled: October 28, 2018Date of Patent: June 30, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Kai-Hsiang Wang, Chao-Nan Chen, Shi-You Liu, Chun-Wei Yu, Yu-Ren Wang
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Patent number: 10651174Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.Type: GrantFiled: May 14, 2019Date of Patent: May 12, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
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Publication number: 20200144102Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned mask layer is formed on a semiconductor substrate. An isolation trench is formed in the semiconductor substrate by removing a part of the semiconductor substrate. A liner layer is conformally formed on an inner sidewall of the isolation trench. An implantation process is performed to the liner layer. The implantation process includes a noble gas implantation process. An isolation structure is at least partially formed in the isolation trench after the implantation process. An etching process is performed to remove the patterned mask layer after forming the isolation structure and expose a top surface of the semiconductor substrate. A part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process. The implantation process is configured to modify the etch rate of the liner layer in the etching process.Type: ApplicationFiled: November 6, 2018Publication date: May 7, 2020Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Shi-You Liu, Shao-Hua Hsu
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Publication number: 20200135922Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.Type: ApplicationFiled: November 30, 2018Publication date: April 30, 2020Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Chun-Wei Yu, Yu-Ren Wang
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Patent number: 10622481Abstract: A method of rounding corners of a fin includes providing a substrate with a fin protruding from the substrate, wherein a pad oxide and a pad nitride entirely cover a top surface of the fin. Later, part of the pad oxide is removed laterally to expose part of the top surface of the fin. A silicon oxide layer is formed to contact two sidewalls of the fin and the exposed top surface, wherein two sidewalls and the top surface define two corners of the fin. After forming the silicon oxide layer, an annealing process is performed to round two corners of the fin. Finally, after the annealing process, an STI filling material is formed to cover the pad nitride, the pad oxide and the fin.Type: GrantFiled: August 7, 2018Date of Patent: April 14, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Hao-Hsuan Chang, Chia-Wei Hsu
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Publication number: 20200098916Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.Type: ApplicationFiled: October 28, 2018Publication date: March 26, 2020Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Kai-Hsiang Wang, Chao-Nan Chen, Shi-You Liu, Chun-Wei Yu, Yu-Ren Wang
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Publication number: 20200052123Abstract: A method of rounding corners of a fin includes providing a substrate with a fin protruding from the substrate, wherein a pad oxide and a pad nitride entirely cover a top surface of the fin. Later, part of the pad oxide is removed laterally to expose part of the top surface of the fin. A silicon oxide layer is formed to contact two sidewalls of the fin and the exposed top surface, wherein two sidewalls and the top surface define two corners of the fin. After forming the silicon oxide layer, an annealing process is performed to round two corners of the fin. Finally, after the annealing process, an STI filling material is formed to cover the pad nitride, the pad oxide and the fin.Type: ApplicationFiled: August 7, 2018Publication date: February 13, 2020Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Hao-Hsuan Chang, Chia-Wei Hsu
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Publication number: 20200051071Abstract: The present invention is related to an electronic transaction system using a blockchain to store transaction records. The electronic transaction system includes a computing device having a verification module, a processing module and a broadcasting module, and the blockchain includes a plurality of user nodes connecting to the computing device. The verification module is configured to generate notification information according to a transaction event, and the notification information is transmitted to a first and second user nodes. The processing module is configured to generate a first and second transaction currency values, the sum of which is zero, after the verification module receives the verification information from the first and second user nodes. The broadcasting module is configured to record transaction information associated with the transferring of the first and second transaction currency values in a data block, and to broadcast the data block to each of user nodes.Type: ApplicationFiled: July 25, 2018Publication date: February 13, 2020Inventors: Ching Song WU, Chun-Wei YU