Patents by Inventor Chun-Wen Hsiao
Chun-Wen Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960762Abstract: A method for managing a memory buffer, a memory control circuit unit, and a memory storage apparatus are provided. The method includes the following steps. Multiple consecutive first commands are received from a host system. A command ratio of read command among the first commands is calculated. The memory storage apparatus is being configured in a first mode or a second mode according to the command ratio and a ratio threshold. A first buffer is configured in a buffer memory to temporarily store a logical-to-physical address mapping table in response to the memory storage device being configured in the first mode, in which the first buffer has a first capacity. A second buffer is configured in the buffer memory in response to the memory storage device being configured in the second mode, in which the second buffer has a second capacity, which is greater than the first capacity.Type: GrantFiled: August 12, 2021Date of Patent: April 16, 2024Assignee: PHISON ELECTRONICS CORP.Inventors: Po-Wen Hsiao, Chun Hao Lin
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Patent number: 11942373Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.Type: GrantFiled: May 10, 2023Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chu-An Lee, Chen-Hao Wu, Peng-Chung Jangjian, Chun-Wen Hsiao, Teng-Chun Tsai, Huang-Lin Chao
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Publication number: 20240088236Abstract: In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Wen HSIAO, Chun-Yen TAI, Yen-Hsin LIU, Ming-Jhih KUO, Ming-Feng SHIEH
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Publication number: 20230271298Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.Type: ApplicationFiled: May 5, 2023Publication date: August 31, 2023Inventors: Michael Yen, Kao-Feng Liao, Hsin-Ying Ho, Chun-Wen Hsiao, Sheng-Chao Chuang, Ting-Hsun Chang, Fu-Ming Huang, Chun-Chieh Lin, Peng-Chung Jangjian, Ji James Cui, Liang-Guang Chen, Chih Hung Chen, Kei-Wei Chen
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Publication number: 20230274982Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.Type: ApplicationFiled: May 10, 2023Publication date: August 31, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chu-An LEE, Chen-Hao WU, Peng-Chung JANGJIAN, Chun-Wen HSIAO, Teng-Chun TSAI, Huang-Lin CHAO
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Patent number: 11688644Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate. A first gate structure and a second gate structure are across the first and second fins, respectively. An insulating structure is formed between the first gate structure and the second gate structure and includes a first insulating layer separating the first fin from the second fin, a capping structure formed in the first insulating layer, and a second insulating layer covered by the first insulating layer and the capping structure.Type: GrantFiled: April 30, 2021Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chu-An Lee, Chen-Hao Wu, Peng-Chung Jangjian, Chun-Wen Hsiao, Teng-Chun Tsai, Huang-Lin Chao
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Patent number: 11679469Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.Type: GrantFiled: August 23, 2019Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Michael Yen, Kao-Feng Liao, Hsin-Ying Ho, Chun-Wen Hsiao, Sheng-Chao Chuang, Ting-Hsun Chang, Fu-Ming Huang, Chun-Chieh Lin, Peng-Chung Jangjian, Ji James Cui, Liang-Guang Chen, Chih Hung Chen, Kei-Wei Chen
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Patent number: 11189727Abstract: A device includes a semiconductor fin protruding from a substrate, a first gate stack over the semiconductor fin and a second gate stack over the semiconductor fin, a first source/drain region in the semiconductor fin adjacent the first gate stack and a second source/drain region in the semiconductor fin adjacent the second gate stack, a first layer of a first dielectric material on the first gate stack and a second layer of the first dielectric material on the second gate stack, a first source/drain contact on the first source/drain region and adjacent the first gate stack, a first layer of a second dielectric material on a top surface of the first source/drain contact, and a second source/drain contact on the second source/drain region and adjacent the second gate stack, wherein the top surface of the second source/drain contact is free of the second dielectric material.Type: GrantFiled: August 23, 2019Date of Patent: November 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Chung Jangjian, Kao-Feng Liao, Chun-Wen Hsiao, Hsin-Ying Ho, Sheng-Chao Chuang
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Publication number: 20210265222Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate. A first gate structure and a second gate structure are across the first and second fins, respectively. An insulating structure is formed between the first gate structure and the second gate structure and includes a first insulating layer separating the first fin from the second fin, a capping structure formed in the first insulating layer, and a second insulating layer covered by the first insulating layer and the capping structure.Type: ApplicationFiled: April 30, 2021Publication date: August 26, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chu-An LEE, Chen-Hao WU, Peng-Chung JANGJIAN, Chun-Wen HSIAO, Teng-Chun TSAI, Huang-Lin CHAO
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Patent number: 10998239Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate. The semiconductor device structure also includes an insulating structure that includes a first insulating layer formed between and separating from the first fin and the second fin, a second insulating layer embedded in the first insulating layer, a first capping layer formed in the first insulating layer to cover a top surface of the second insulating layer, and a second capping layer in the first capping layer.Type: GrantFiled: July 13, 2020Date of Patent: May 4, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chu-An Lee, Chen-Hao Wu, Peng-Chung Jangjian, Chun-Wen Hsiao, Teng-Chun Tsai, Huang-Lin Chao
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Publication number: 20210057571Abstract: A device includes a semiconductor fin protruding from a substrate, a first gate stack over the semiconductor fin and a second gate stack over the semiconductor fin, a first source/drain region in the semiconductor fin adjacent the first gate stack and a second source/drain region in the semiconductor fin adjacent the second gate stack, a first layer of a first dielectric material on the first gate stack and a second layer of the first dielectric material on the second gate stack, a first source/drain contact on the first source/drain region and adjacent the first gate stack, a first layer of a second dielectric material on a top surface of the first source/drain contact, and a second source/drain contact on the second source/drain region and adjacent the second gate stack, wherein the top surface of the second source/drain contact is free of the second dielectric material.Type: ApplicationFiled: August 23, 2019Publication date: February 25, 2021Inventors: Peng-Chung Jangjian, Kao-Feng Liao, Chun-Wen Hsiao, Hsin-Ying Ho, Sheng-Chao Chuang
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Publication number: 20210053180Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.Type: ApplicationFiled: August 23, 2019Publication date: February 25, 2021Inventors: Michael Yen, Kao-Feng Liao, Hsin-Ying Ho, Chun-Wen Hsiao, Sheng-Chao Chuang, Ting-Hsun Chang, Fu-Ming Huang, Chun-Chieh Lin, Peng-Chung Jangjian, Ji James Cui, Liang-Guang Chen, Chih Hung Chen, Kei-Wei Chen
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Publication number: 20200365588Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate. The semiconductor device structure also includes an insulating structure that includes a first insulating layer formed between and separating from the first fin and the second fin, a second insulating layer embedded in the first insulating layer, a first capping layer formed in the first insulating layer to cover a top surface of the second insulating layer, and a second capping layer in the first capping layer.Type: ApplicationFiled: July 13, 2020Publication date: November 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chu-An LEE, Chen-Hao WU, Peng-Chung JANGJIAN, Chun-Wen HSIAO, Teng-Chun TSAI, Huang-Lin CHAO
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Patent number: 10714395Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate, an isolation feature between and adjacent to the first fin and the second fin, and a fin isolation structure between the first fin and the second fin. The fin isolation structure includes a first insulating layer partially embedded in the isolation feature, a second insulating layer having sidewall surfaces and a bottom surface that are covered by the first insulating layer, a first capping layer covering the second insulating layer and having sidewall surfaces that are covered by the first insulating layer, and a second capping layer having sidewall surfaces and a bottom surface that are covered by the first capping layer.Type: GrantFiled: February 15, 2019Date of Patent: July 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chu-An Lee, Chen-Hao Wu, Peng-Chung Jangjian, Chun-Wen Hsiao, Teng-Chun Tsai, Huang-Lin Chao
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Publication number: 20200091007Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate, an isolation feature between and adjacent to the first fin and the second fin, and a fin isolation structure between the first fin and the second fin. The fin isolation structure includes a first insulating layer partially embedded in the isolation feature, a second insulating layer having sidewall surfaces and a bottom surface that are covered by the first insulating layer, a first capping layer covering the second insulating layer and having sidewall surfaces that are covered by the first insulating layer, and a second capping layer having sidewall surfaces and a bottom surface that are covered by the first capping layer.Type: ApplicationFiled: February 15, 2019Publication date: March 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chu-An LEE, Chen-Hao WU, Peng-Chung JANGJIAN, Chun-Wen HSIAO, Teng-Chun TSAI, Huang-Lin CHAO
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Patent number: 9539326Abstract: An (acid-substituted polyaniline)-grafted hydrogel copolymer is provided. The (acid-substituted polyaniline)-grafted hydrogel copolymer has a general formula as below: wherein A is a proton acid group, m and n are same or different integers greater than 0, x is an integer equal to or greater than 0, and y is an integer equal to or greater than 1, provided that x and y are the same or different at each occurrence, and at least an x is not 0. The (acid-substituted polyaniline)-grafted hydrogel copolymer is formed by the polymerization and substitution reaction between chitosan, polyaniline, and proton acid. The (acid-substituted polyaniline)-grafted hydrogel copolymer behaves as a pH-responsive hydrogel with photo-thermal properties and can be applied to photo-thermal therapy.Type: GrantFiled: June 1, 2016Date of Patent: January 10, 2017Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Hsing-Wen Sung, Chun-Wen Hsiao, Chieh-Cheng Huang, Min-Fan Chung, Zi-Xian Liao, Wei-Lun Chiang
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Publication number: 20160271250Abstract: An (acid-substituted polyaniline)-grafted hydrogel copolymer is provided. The (acid-substituted polyaniline)-grafted hydrogel copolymer has a general formula as below: wherein A is a proton acid group, m and n are same or different integers greater than 0, x is an integer equal to or greater than 0, and y is an integer equal to or greater than 1, provided that x and y are the same or different at each occurrence, and at least an x is not 0. The (acid-substituted polyaniline)-grafted hydrogel copolymer is formed by the polymerization and substitution reaction between chitosan, polyaniline, and proton acid. The (acid-substituted polyaniline)-grafted hydrogel copolymer behaves as a pH-responsive hydrogel with photo-thermal properties and can be applied to photo-thermal therapy.Type: ApplicationFiled: June 1, 2016Publication date: September 22, 2016Inventors: Hsing-Wen Sung, Chun-Wen Hsiao, Chieh-Cheng Huang, Min-Fan Chung, Zi-Xian Liao, Wei-Lun Chiang
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Publication number: 20160000919Abstract: An (acid-substituted polyaniline)-grafted hydrogel copolymer is provided. The (acid-substituted polyaniline)-grafted hydrogel copolymer has a general formula as below: The A is a proton acid group. The (acid-substituted polyaniline)-grafted hydrogel copolymer is formed by the polymerization and substitution reaction between chitosan, polyaniline, and proton acid. The (acid-substituted polyaniline)-grafted hydrogel copolymer behaves as a pH-responsive hydrogel with photo-thermal properties and can be applied to photo-thermal therapy.Type: ApplicationFiled: September 17, 2014Publication date: January 7, 2016Inventors: Hsing-Wen Sung, Chun-Wen Hsiao, Chieh-Cheng Huang, Min-Fan Chung, Zi-Xian Liao, Wei-Lun Chiang