Abstract: A semiconductor device includes a first semiconductor structure, a second semiconductor structure, a first isolation block and a second isolation block. The first semiconductor structure includes a first gate structure wrapping around a first sheet structures and a second sheet structures, and a first dielectric wall disposed between and separating the first and second sheet structures. The second semiconductor structure includes a second gate structure wrapping around third sheet structures. The first isolation block is disposed on the first dielectric wall of the first semiconductor structure and separates the first gate structure into a first gate portion wrapping around the first sheet structures and a second gate portion wrapping around the second sheet structures. The second isolation block is disposed between the first and second semiconductor structures and separates the first gate structure from the second gate structure.

Abstract: A semiconductor device includes a first diffusion region having a first conductivity type, a first SiGe fin formed on the first diffusion region, a second diffusion region having a second conductivity type, and a second SiGe fin formed on the second diffusion region and including a central portion including a first amount of Ge, and a surface portion including a second amount of Ge which is greater than the first amount. A total width of the central portion and the surface portion is substantially equal to a width of the second diffusion region.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: A semiconductor device and method for forming the same. The device comprises at least a dielectric layer, a two-dimensional (2D) material layer, a gate structure, and source/drain contacts. The 2D material layer contacts the dielectric layer. The gate structure contacts the 2D material layer. The source/drain contacts are disposed above the 2D material layer and contact the gate structure. The method includes forming a structure including at least a handle wafer, a 2D material layer, a gate structure in contact with the 2D material layer, an insulating layer, and a sacrificial layer. A portion of the sacrificial layer is etched. An inter-layer dielectric is formed in contact with the insulating layer and sidewalls of the sacrificial layer. The sacrificial layer and a portion of the insulating layer are removed. Source and drain contacts are formed in contact with the portion of the 2D material layer.

Abstract: An approach for utilizing an IC (integrated circuit) that is capable of storing multi-bit in storage is disclosed. The approach leverages the use of multiple nanowires structures as channels in a gate of a transistor. The use of multiple nanowires as channels allows for different Vt (i.e., voltage of device) to be dependent on the thickness of the fe (ferroelectric layer) that surrounds each of the nanowire channels. Memory window is about 2d (thickness of a fe layer). Setting voltage is also proportional to the fe layer thickness. The Vt of the device is the superposition of the various fe layers. For example, if there are three channels with three different Fe layer (of varying thickness), then four memory states can be achieved. More states can be achieved based on the number of channels in the device.

Abstract: Forming a first opening in a first double stacked fin and forming a second opening in a second double stacked fin, by removing a high silicon germanium layer, forming a low k spacer, removing a dummy gate, and removing portions of the low k spacer from an outer surface of the first double stacked fin, and an outer surface of the second double stacked fin. A structure including an upper fin of a double stacked fin separated from a lower fin of a double stacked fin by a low k spacer and by a p type field effect transistor work function metal layer (PFET WFM), where a horizontal lower surface of the upper fin is coplanar with a horizontal upper surface of the low k spacer and a horizontal lower surface of the low k spacer is coplanar with a horizontal upper surface of the PFET WFM.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: A semiconductor device and method for forming the same. The device comprises at least a dielectric layer, a two-dimensional (2D) material layer, a gate structure, and source/drain contacts. The 2D material layer contacts the dielectric layer. The gate structure contacts the 2D material layer. The source/drain contacts are disposed above the 2D material layer and contact the gate structure. The method includes forming a structure including at least a handle wafer, a 2D material layer, a gate structure in contact with the 2D material layer, an insulating layer, and a sacrificial layer. A portion of the sacrificial layer is etched. An inter-layer dielectric is formed in contact with the insulating layer and sidewalls of the sacrificial layer. The sacrificial layer and a portion of the insulating layer are removed. Source and drain contacts are formed in contact with the portion of the 2D material layer.

Abstract: Semiconductor device structures and techniques are provided for measuring contact resistance. A semiconductor device is disclosed including a first source/drain region and a contact disposed on the first source/drain region and configured to supply energy to the semiconductor device. A fin extends between the first source/drain region and a second source/drain region of the semiconductor device. A first contact material layer is disposed on the second source/drain region and a first active drain contact is disposed on the first contact material layer. A first sensor drain contact is also disposed on the first contact material layer. A second contact material layer is disposed on the second source/drain region and a second active drain contact is disposed on the second contact material layer. A third contact material layer is disposed on the second source/drain region and a second sensor drain contact is disposed on the third contact material layer.

Abstract: A semiconductor device includes a semiconductor wafer having one or more suspended nanosheet extending between first and second source/drain regions. A gate structure wraps around the nanosheet stack to define a channel region located between the source/drain regions. The semiconductor device further includes a first all-around source/drain contact formed in the first source/drain region and a second all-around source/drain contact formed in the second source/drain region. The first and second all-around source/drain contacts each include a source/drain epitaxy structure and an electrically conductive external portion that encapsulates the source/drain epitaxy structure.

Abstract: A semiconductor device and method for forming the same. The device comprises at least a dielectric layer, a two-dimensional (2D) material layer, a gate structure, and source/drain contacts. The 2D material layer contacts the dielectric layer. The gate structure contacts the 2D material layer. The source/drain contacts are disposed above the 2D material layer and contact the gate structure. The method includes forming a structure including at least a handle wafer, a 2D material layer, a gate structure in contact with the 2D material layer, an insulating layer, and a sacrificial layer. A portion of the sacrificial layer is etched. An inter-layer dielectric is formed in contact with the insulating layer and sidewalls of the sacrificial layer. The sacrificial layer and a portion of the insulating layer are removed. Source and drain contacts are formed in contact with the portion of the 2D material layer.

Abstract: A method of forming a semiconductor structure includes forming at least one fin disposed over a substrate, wherein sidewalls of the at least one fin includes a first portion proximate a top surface of the substrate having a tapered profile and a second portion disposed above the first portion. The method also includes forming a bottom source/drain region surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile and forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding at least part of the second portion of the sidewalls of the at least one fin. The at least one fin provides a channel for a vertical field-effect transistor.

Abstract: Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.

Abstract: Forming a first opening in a first double stacked fin and forming a second opening in a second double stacked fin, by removing a high silicon germanium layer, forming a low k spacer, removing a dummy gate, and removing portions of the low k spacer from an outer surface of the first double stacked fin, and an outer surface of the second double stacked fin. A structure including an upper fin of a double stacked fin separated from a lower fin of a double stacked fin by a low k spacer and by a p type field effect transistor work function metal layer (PFET WFM), where a horizontal lower surface of the upper fin is coplanar with a horizontal upper surface of the low k spacer and a horizontal lower surface of the low k spacer is coplanar with a horizontal upper surface of the PFET WFM.

Abstract: A method is presented for forming a transistor having reduced parasitic contact resistance. The method includes forming a first device over a semiconductor structure, forming a second device adjacent the first device, forming an ILD over the first and second devices, and forming recesses within the ILD to expose the source/drain regions of the first device and the source/drain regions of the second device. The method further includes forming a first dielectric layer over the ILD and the top surfaces of the source/drain regions of the first and second devices, a chemical interaction between the first dielectric layer and the source/drain regions of the second device resulting in second dielectric layers formed over the source/drain regions of the second device, and forming an epitaxial layer over the source/drain regions of the first device after removing remaining portions of the first dielectric layer.

Abstract: A method of forming a vertical transport fin field effect transistor is provided. The method includes forming a doped layer on a substrate, and forming a multilayer fin on the doped layer, where the multilayer fin includes a lower trim layer portion, an upper trim layer portion, and a fin channel portion between the upper and lower trim layer portions. A portion of the lower trim layer portion is removed to form a lower trim layer post, and a portion of the upper trim layer portion is removed to form an upper trim layer post. An upper recess filler is formed adjacent to the upper trim layer post, and a lower recess filler is formed adjacent to the lower trim layer post. A portion of the fin channel portion is removed to form a fin channel post between the upper trim layer post and lower trim layer post.

Abstract: A method of fabricating a vertically stacked nanosheet semiconductor device includes epitaxially growing at least three layers each of alternating silicon and silicon germanium layers on a substrate and patterning a gate structure. The method includes performing at least three reactive ion etch processes forming recesses. The method includes forming source or drain regions in a channel formed by a shallow trench isolation layer formed in the recesses. The method includes growing a first epitaxial layer on the source or drain regions, forming at least three pFET structures. The method includes etching away a portion of each of the pFET structures and depositing a dielectric layer on each. The method includes growing a second epitaxial layer, forming at least three nFET structures. Each layer of the pFET structure and nFET structure are stacked vertically and each layer of the pFET structure and nFET structures have independent source or drain contacts.

Abstract: Semiconductor device structures and techniques are provided for measuring contact resistance. A semiconductor device is disclosed including a first source/drain region and a contact disposed on the first source/drain region and configured to supply energy to the semiconductor device. A fin extends between the first source/drain region and a second source/drain region of the semiconductor device. A first contact material layer is disposed on the second source/drain region and a first active drain contact is disposed on the first contact material layer. A first sensor drain contact is also disposed on the first contact material layer. A second contact material layer is disposed on the second source/drain region and a second active drain contact is disposed on the second contact material layer. A third contact material layer is disposed on the second source/drain region and a second sensor drain contact is disposed on the third contact material layer.