Patents by Inventor Chun Won Byun

Chun Won Byun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120007158
    Abstract: Provided is a non-volatile memory transistor having a double gate structure, including a first gate electrode formed on a substrate and to which an operating voltage is applied, a first gate insulating layer formed on the first gate electrode, source and drain electrodes formed on the first gate insulating layer at predetermined intervals, a channel layer formed on the first gate insulating layer between the source and drain electrodes, a second gate insulating layer formed on the channel layer, and a second gate electrode formed on the second gate insulating layer and connected to the first gate electrode such that the operating voltage is applied thereto. Accordingly, a turn-on voltage of the memory transistor can be easily controlled.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 12, 2012
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung Min YOON, Shin Hyuk Yang, Chun Won Byun, Min Ki Ryu, Soon Won Jung
  • Publication number: 20110305062
    Abstract: Provided are a memory cell and a memory device using the same, particularly, a nonvolatile non-destructive readable random access memory cell including a ferroelectric transistor as a storage unit and a memory device using the same. The memory cell includes a ferroelectric transistor having a drain to which a reference voltage is applied, a first switch configured to allow a source of the ferroelectric transistor to be connected to a first line in response to a scan signal, and a second switch configured to allow a gate of the ferroelectric transistor to be connected to a second line in response to the scan signal. The memory device enables random access and performs non-destructive read-out (NDRO) operations.
    Type: Application
    Filed: September 21, 2010
    Publication date: December 15, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chun Won BYUN, Byeong Hoon Kim, Sung Min Yoon, Kyoung Ik Cho, Sang Hee Park, Chi Sun Hwang, Min Ki Ryu, Shin Hyuk Yang, Oh Sang Kwon, Eun Suk Park
  • Publication number: 20110253997
    Abstract: Provided is a semiconductor device using a p-type oxide semiconductor layer and a method of manufacturing the same. The device includes the p-type oxide layer formed of at least one oxide selected from the group consisting of a copper(Cu)-containing copper monoxide, a tin(Sn)-containing tin monoxide, a copper tin oxide containing a Cu—Sn alloy, and a nickel tin oxide containing a Ni—Sn alloy. Thus, transparent or opaque devices are easily developed using the p-type oxide layer. Since an oxide layer that is formed using a low-temperature process is applied to a semiconductor device, the manufacturing process of the semiconductor device is simplified and manufacturing costs may be reduced.
    Type: Application
    Filed: April 14, 2011
    Publication date: October 20, 2011
    Applicants: FACULTY OF SCIENCE AND TECHNOLOGY NEW UNIVERSITY OF LISBON, ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sang Hee Park, Chi Sun Hwang, Chun Won Byun, Elvira M.C. Fortunato, Rodrigo F.P. Martins, Ana R.X. Barros, Nuno F.O. Correia, Pedro M.C. Barquinha, Vitor M.L. Figueiredo
  • Patent number: 8017045
    Abstract: Provided is a composition for an oxide semiconductor thin film and a field effect transistor (FET) using the composition. The composition includes from about 50 to about 99 mol % of a zinc oxide (ZnO); from about 0.5 to 49.5 mol % of a tin oxide (SnOx); and remaining molar percentage of an aluminum oxide (AlOx). The thin film formed of the composition remains in amorphous phase at a temperature of 400° C. or less. The FET includes an active layer formed of the composition and has improved electrical characteristics. The FET can be fabricated using a low-temperature process without expensive raw materials, such as In and Ga.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: September 13, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Doo Hee Cho, Shin Hyuk Yang, Chun Won Byun, Chi Sun Hwang, Hye Yong Chu, Kyoung Ik Cho
  • Publication number: 20110095702
    Abstract: A stacked organic light-emitting device is provided. The stacked organic light-emitting device includes a first electrode, first and second light-emitting units formed under and on the first electrode respectively, transparent or semi-transparent second and third electrodes formed under the first light-emitting unit and on the second light-emitting unit respectively, and having the same polarity, and a drive controller electrically connected with the first, second and third electrodes to connect the first and second light-emitting units in parallel, and capable of controlling at least one of the first and second light-emitting units to emit light. Accordingly, the organic light-emitting device has a lower driving voltage than a conventional stacked light-emitting device in which light-emitting units are serially connected.
    Type: Application
    Filed: February 22, 2010
    Publication date: April 28, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jeong Ik Lee, Jong Hee Lee, Chun Won Byun, Hye Yong Chu
  • Publication number: 20110049592
    Abstract: Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.
    Type: Application
    Filed: July 19, 2010
    Publication date: March 3, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung Min YOON, Chun Won BYUN, Shin Hyuk YANG, Sang Hee PARK, Soon Won JUNG, Seung Youl KANG, Chi Sun HWANG, Byoung Gon YUN
  • Publication number: 20100243994
    Abstract: Provided are a transparent nonvolatile memory thin film transistor (TFT) and a method of manufacturing the same. The memory TFT includes source and drain electrodes disposed on a transparent substrate. A transparent semiconductor thin layer is disposed on the source and drain electrodes and the transparent substrate interposed between the source and drain electrodes. An organic ferroelectric thin layer is disposed on the transparent semiconductor thin layer. A gate electrode is disposed on the organic ferroelectric thin layer in alignment with the transparent semiconductor thin layer. Thus, the transparent nonvolatile memory TFT employs the organic ferroelectric thin layer, the oxide semiconductor thin layer, and auxiliary insulating layers disposed above and below the organic ferroelectric thin layer, thereby enabling low-cost manufacture of a transparent nonvolatile memory device capable of a low-temperature process.
    Type: Application
    Filed: September 9, 2009
    Publication date: September 30, 2010
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sung Min Yoon, Shin Hyuk Yang, Soon Woon Jung, Seung Youl Kang, Doo Hee Cho, Chun Won Byun, Chi Sun Hwang, Byoung Gon Yu, Kyoung Ik Cho
  • Publication number: 20100155792
    Abstract: Provided is a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. Here, the lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel. Thus, the use of the multi-layered transparent conductive layer can ensure transparency and conductivity, overcome a problem of contact resistance between the source and drain electrodes and a semiconductor, and improve processibility by patterning the multi-layered transparent conductive layer all at once, while deposition is performed layer by layer.
    Type: Application
    Filed: September 4, 2009
    Publication date: June 24, 2010
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Min Ki Ryu, Chi Sun Hwang, Chun Won Byun, Hye Yong Chu, Kyong Ik Cho
  • Publication number: 20100006837
    Abstract: Provided are a composition for an oxide semiconductor thin film, a field effect transistor using the same and a method of fabricating the field effect transistor. The composition includes an aluminum oxide, a zinc oxide, an indium oxide and a tin oxide. The thin film formed of the composition is in amorphous phase. The field effect transistor having an active layer formed of the composition can have an improved electrical characteristic and be fabricated by a low temperature process.
    Type: Application
    Filed: July 1, 2009
    Publication date: January 14, 2010
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Doo Hee Cho, Sang Hee Park, Chi Sun Hwang, Hye Yong Chu, Kyoung Ik Cho, Shin Hyuk Yang, Chun Won Byun, Eun Suk Park, Oh Sang Kwon, Min Ki Ryu, Jae Heon Shin, Woo Seok Cheong, Sung Mook Chung, Jeong Ik Lee
  • Publication number: 20090261389
    Abstract: A composition for an oxide semiconductor thin film, a field effect transistor (FET) using the composition, and a method of fabricating the FET are provided. The composition includes an aluminum oxide, a zinc oxide, and a tin oxide. The thin film formed of the composition remains in amorphous phase at a temperature of 400° C or less. The FET using an active layer formed of the composition has improved electrical characteristics and can be fabricated using a low-temperature process without expensive raw materials, such as In and Ga.
    Type: Application
    Filed: December 10, 2008
    Publication date: October 22, 2009
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Doo Hee Cho, Shin Hyuk Yang, Chun Won Byun, Chi Sun Hwang, Hye Yong Chu, Kyoung Ik Cho