Abstract: A terahertz wave detection chip includes a substrate and at least one detection structure. The detection structure is disposed on a surface of the substrate. The detection structure includes a metamaterial layer and a hydrophilic layer, and the hydrophilic layer is disposed on the metamaterial layer.

Abstract: A circuit for data processing is provided. The circuit comprises a dual-mode adder, a max finder circuit, a zone detector circuit and an alignment circuit. The dual-mode adder generates products between first exponents of first floating point numbers and second exponents of second floating point numbers. The max finder circuit finds a maximum among first portions of the products. The zone detector circuit classify the first portions into zones by comparing the first portions and the maximum. The alignment circuit align first mantissas of the first floating point numbers according to the zones and second portions of the products to generate aligned mantissas for a floating point number operation.

Abstract: A method for enhancing an accuracy of a benign tumor development trend assessment system includes: a first processing procedure, an image captured before the treatment is inputted to and be processed by a server computing device of the benign tumor development trend assessment system to obtain a first processing result; a second processing procedure, the images captured before and in at least one period after the treatment are inputted to and processed by the server computing device to obtain a second processing result; a trend analyzing procedure, the trend analyzing module of the server computing device analyzes the first processing result, the second processing result and the trend pathways to obtain a tumor development trend result; and a storing procedure, the first processing result, the second processing result and the tumor development trend result are transformed to an individual trend pathway which is stored in the trend analyzing module.

Abstract: An electrical connector and assembly are provided. The electrical connector includes an insulative base and terminal columns. Each terminal column includes ground terminals and differential signal terminal pairs, the terminal columns are spaced apart from each other. Each ground terminal has a body portion and three elastic contact portions. Each signal terminal of each differential signal terminal pair has a body portion and an elastic contact portion. In two adjacent terminal columns, orthographic projections of the two elastic contact portions of each differential signal terminal pair are positioned within a range defined by a width of the elastic contact portions of the corresponding ground terminal, and an orthographic projection of the elastic contact portion positioned in a middle of each around terminal in the second direction is positioned within a range defined by a width of the two elastic contact portions of the corresponding differential signal terminal pair.

Abstract: A fastener stop structure includes a first stop portion and a second stop portion. An inner lateral surface of the first stop portion facing the second stop portion is provided with a protruding portion. A size of a portion of the first stop portion where the protruding portion is disposed in a width direction is greater than a size of an element channel of the slider used in a fastener chain in the width direction, and the protruding portion is disposed at a distance from a front end edge of the first stop portion in a length direction. The fastener includes the fastener chain, the slider, and the fastener stop structure. When the slider slides on a pair of element columns along the length direction, the first stop portion and the second stop portion of the fastener stop structure are able to enter the pair of element channels.

Abstract: Provided is a promoter sequence induced by methyl jasmonate. Also provided are an expression cassette, a recombinant vector and a recombinant cell comprising the promoter sequence. In addition, further provided is a method for producing an exogenous protein using the expression vector, and in particular a method for producing a human elastin in a rice cell using the expression vector. Further provided is a skin care composition comprising the exogenous protein. The composition is not cytotoxic to HaCaT cell lines and CCD966SK cell lines, and can increase the expression levels of water retention-related genes hHAS2, hHAS3, hAQP3 and hFLG in a cell, thereby improving the water retention and barrier functions in the cell as well as having a broad application prospect.

Abstract: In this disclosure, a storage circuit is provided. The storage circuit includes a gain-cell, a self-refresh unit, and a latch circuit. The gain-cell is configured to store first data in a gate of a storage transistor. The self-refresh unit is configured to read the first data from the gain-cell and write the first data back to the gain-cell. The latch circuit is configured to read the first data from the self-refresh unit and latch the first data.

Abstract: An IC device manufacturing method includes forming first and second active areas in a first row extending in a first direction and third and fourth active areas in a second, adjacent row, each including S/D structures, constructing first and second conductive segments extending in a second direction overlying and electrically connected to a S/D structure in each of the second and third active areas, constructing additional conductive segments, gates, and vias to form an AOI, OAI, or four-input NAND including the first and second segments and pull-up and pull-down transistors in each of the first and second rows, and constructing first through third power rails extending in the first direction, the first and second and second and third power rails aligned with the respective first and second rows. The first and second segments cross a plane perpendicular to the first and second conductive segments and including the second power rail.

Abstract: A detection apparatus configured for PCR testing includes a carrier structure and a temperature detection module. The carrier structure is configured to carry a test tube, and the test tube is configured for containing a reagent and a specimen. The temperature detection module is disposed on the carrier structure and includes a heat transfer medium and a temperature sensor. The heat capacity of the heat transfer medium is approximately equal to a preset value, so as to match heat capacity of the reagent. The temperature sensor is configured to sense a temperature of the heat transfer medium. In addition, a method for detecting a temperature of the detection apparatus is also provided.

Abstract: The present disclosure provides a display structure. The display structure includes a display layer, a reflective polarizing layer, a dispersed liquid crystal layer and a pattern layer. The reflective polarizing layer is disposed at a side of the display layer. The dispersed liquid crystal layer is disposed at a side of the reflective polarizing layer away from the display layer. The pattern layer is disposed at a side of the dispersed liquid crystal layer away from the reflective polarizing layer. The combination of the reflective polarizing layer and the dispersed liquid crystal layer can prevent the pattern layer from affecting the overall display effect of the display layer when the display layer is turned on. The visual effect of the pattern layer can be also enhanced when the display layer is turned off.

Abstract: An electronic device with dynamic lighting effect and a method for generating dynamic lighting effect are provided. The method for generating dynamic lighting effect includes the following steps. A lighting effect tracking frame is provided according to an eye position of a user, a dynamic lighting effect frame is received, or a predefined lighting effect frame is stored. The lighting effect tracking frame, the dynamic lighting effect frame or the predefined lighting effect frame is obtained. A size adjustment procedure is performed on the lighting effect tracking frame, the dynamic lighting effect frame or the predefined lighting effect frame to obtain a lighting effect control map. The dynamic lighting effect device is controlled according to the lighting effect control map to generate the dynamic lighting effect.

Abstract: A microfluidic sensor chip includes a body comprising a substrate and an upper cover, and the upper cover having at least one opening, at least one microfluidic channel formed on the substrate and has a supporting surface, wherein the at least one microfluidic channel communicates with the at least one opening, and a metamaterial layer coated on the supporting surface, wherein the metamaterial layer has a plurality of regions, and each region has a corresponding resonance pattern. The present disclosure further provides a measuring system for microfluidic sensor chip includes a carrying board, a plurality of the microfluidic sensor chips, a transmitter emitting a terahertz wave corresponding to the resonance pattern of one of the microfluidic sensor chips, a receiver receiving a reflected wave corresponding to the terahertz wave, and a processor receiving the reflected wave from the processor, and determining a testing sample characteristic according to the reflected wave.

Abstract: An apparatus includes a wafer stage and a particle removing assembly. The wafer stage includes a cup adjacent to a wafer chuck. The particle removing assembly is configured to remove contaminant particles from the cup. In some embodiments, the particle removing assembly comprises a flexible ejecting member that includes one or more elongated tubes, a front tip, and a cleaning tip adapter configured to attach the front tip to each of the one or more elongated tubes. The front tip includes front openings and lateral openings from which pressurized cleaning material are introduced onto an unreachable area of the cup to remove the contaminant particles from the cup.

Abstract: The present invention provides a trademark risk management system and method, which is implemented by providing a user-operated electronic device, wherein the electronic device comprises a processor and a network interface controller, a server comprises an application, and the processor connects to the server through the network interface controller to execute the application for the purpose of category recommendation and risk management, especially for the regeneration of text or graphics.

Abstract: A battery includes a case, in which a battery module, a battery management system and a junction terminal block are received. The battery module has cell blocks electrically connected in series, and each of the cell blocks has electrodes. The junction terminal block has a plurality of junction terminals to be electrically connected to the electrodes of the cell blocks through a plurality of junction wires respectively. The battery further has an external connector having a plurality of external terminals to be electrically connected to the junction terminals of the junction terminal block through a plurality of external wires. The external terminals of the external connector are electrically connected to the cell blocks through the external wires, the junction terminals of the junction terminal block and the junction wires respectively, so that all the cell blocks are able to be charged individually through the external connector.

Abstract: A method for forming a semiconductor device structure includes forming nanostructures over a substrate. The method also includes forming a gate structure wrapped around the nanostructures. The method also includes forming source/drain epitaxial structures over opposite sides of the nanostructures. The method also includes forming an interlayer dielectric structure over the source/drain epitaxial structures. The method also includes etching the interlayer dielectric structure to form an opening exposing the source/drain epitaxial structures. The method also includes depositing a first spacer layer over sidewalls of the interlayer dielectric structure in the opening. The method also includes forming a silicide structure over the source/drain epitaxial structures. The method also includes forming a bottom contact structure over the silicide structure. The method also includes depositing a second spacer layer over the first spacer layer.

Abstract: A memory system comprising a memory device including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches coupled to the bit lines, and configured to program input data stored in the latches into memory cells of a selected word line during a program operation, and output, as information data, at least one or more data among first data stored in the latches and second data stored in the memory cells of the selected word line during a program suspend operation for suspending the program operation, and a controller configured to repair the input data by performing a set logic operation on the information data from the memory device, and apply the set logic operation whose type is different according to an execution moment of the program suspend operation.

Abstract: An information handling system includes an air mover and a management controller configured to determine an airflow direction of the air mover. The air mover includes an enclosure base and a gear disposed within the enclosure base. The gear is configured to rotate an outlet frame, and the outlet frame is configured to rotate within the enclosure base. The outlet frame includes a nozzle structure that is configured to guide the airflow direction according to a determination of the management controller.

Abstract: An IC device includes first and second power rails extending in a first direction and carrying one of a power supply or reference voltage, a third power rail extending between the first and second power rails and carrying the other of the power supply or reference voltage, and a plurality of transistors including first through fourth active areas extending between the first and second power rails, a plurality of gate structures extending perpendicularly to the first direction, and first and second conductive segments extending in the second direction across the third power rail. Each of the second and third active areas is adjacent to the third power rail, each of the first and second conductive segments is electrically connected to S/D structures in each of the second and third active areas, and the plurality of transistors is configured as one of an AOI, an OAI, or a four-input NAND gate.

Abstract: Memory systems and operating method of a memory system are provided. The memory system utilized for performing a computing-in-memory (CiM) operation comprises a memory array and a processing circuit. The memory array comprises a plurality of memory cells. The processing circuit is coupled to the memory array and comprises a programming circuit and a control circuit. The programming circuit is coupled to the memory array and configured to perform a write operation for programming electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operation performed by the programming circuit, so the electrical characteristics of the memory cells are programmed following a sequential order of the weight values.