Abstract: A time-of-flight sensor includes a substrate, a single photon avalanche detection chip, a vertical cavity surface-emitting laser, a first narrowband pass filter glass, and a second narrowband pass filter glass and a resin shell. The single photon avalanche detection chip is attached on the substrate, and the vertical cavity surface-emitting laser is also attached on the substrate. The first narrowband pass filter glass is arranged above the single photon avalanche detection chip, and the second narrowband pass filter glass is arranged above the vertical cavity surface-emitting laser. The resin shell covers the first narrowband pass filter glass and the second narrowband pass filter glass, and an upper surface of the first narrowband pass filter glass and an upper surface of the second narrowband pass filter glass are coplanar with an upper surface of the resin shell.

Abstract: A self-tuning model compression methodology for reconfiguring a Deep Neural Network (DNN) includes: receiving a pre-trained DNN model and a data set; performing an inter-layer sparsity analysis to generate a first sparsity result; and performing an intra-layer sparsity analysis to generate a second sparsity result, including: defining a plurality of sparsity metrics for the network; performing forward and backward passes to collect data corresponding to the sparsity metrics; using the collected data to calculate values for the defined sparsity metrics; and visualizing the calculated values using at least a histogram.

Abstract: A stacked semiconductor package has a substrate, a first chip, at least one spacer, a second chip and an encapsulation. The first chip and the second chip are intersecting stacked on the substrate. The at least one spacer is stacked on the substrate to support the second chip. The encapsulation is formed to encapsulate the substrate, the first chip, the at least one spacer and the second chip. The at least one spacer is made of the material of the encapsulation. Therefore, the adhesion between the at least one spacer and the encapsulation is enhanced to avoid the delamination during the reliability test and enhances the reliability of the stacked semiconductor package.

Abstract: A stacked semiconductor package has a substrate, a first chip, at least one spacer, a second chip and an encapsulation. The first chip and the second chip are intersecting stacked on the substrate. The at least one spacer is stacked on the substrate to support the second chip. The encapsulation is formed to encapsulate the substrate, the first chip, the at least one spacer and the second chip. The at least one spacer is made of the material of the encapsulation. Therefore, the adhesion between the at least one spacer and the encapsulation is enhanced to avoid the delamination during the reliability test and enhances the reliability of the stacked semiconductor package.