Patents by Inventor Chun Y. Chang

Chun Y. Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6180419
    Abstract: A method for manufacturing a magnetic field transducing device is provided which includes (a) providing a substrate, (b) subjecting the substrate to a semiconductor device fabricating process in order to obtain a magnetic field transducer, (c) forming an oxide over the magnetic field transducer and (d) covering a magnetic film on the oxide in order to obtain the magnetic field transducing device.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: January 30, 2001
    Assignee: National Science Council
    Inventors: Hsiao-Yi Lin, Tan-Fu Lei, Ci-Lin Pan, Chun Y. Chang, Jz-Jan Jeng
  • Patent number: 5565700
    Abstract: A new surface counter-doped lightly doped source and drain integrated circuit field effect transistor device is described. A gate silicon oxide layer is formed on the silicon substrate. A layer of polysilicon is deposited over the gate silicon oxide layer and etched to form a gate electrode structure. A first ion implantation is performed at a tilt angle to form lightly doped drain regions in the semiconductor substrate wherein the lightly doped drain regions are partially overlapped by the gate electrode structure. A second ion implantation is performed at a larger tilt angle and lower energy than the first ion implantation wherein the second ion implantation counter-dopes the surface of the lightly doped drain regions to form a very lightly doped drain layer thus making the lightly doped drain regions buried regions.
    Type: Grant
    Filed: April 20, 1995
    Date of Patent: October 15, 1996
    Assignee: United Microelectronics Corporation
    Inventors: Jih W. Chou, Joe Ko, Chun Y. Chang
  • Patent number: 5469961
    Abstract: This invention relates to a combined minidisc box, especially a kind of combined minidisc box which can be connected with each other with its left, right, top and bottom sides. The combined minidisc box comprising an upper case and a lower case, wherein the lower case having flanges which can be fitted with grooves of the upper case, two sides of the upper case having respectively a continuous interval dovetails and dovetail slots. Each dovetail and dovetail slots of one side being faced to each dovetail slots and dovetail of the other side, at the top of the upper case having fitting holes and the bottom having fitting posts. The two continuous interval dovetails and dovetail slots of the combined minidisc box can be fitted and connected respectively with continuous interval dovetail slots and dovetails of other combined minidisc boxes.
    Type: Grant
    Filed: August 15, 1994
    Date of Patent: November 28, 1995
    Inventor: Chun Y. Chang
  • Patent number: 5354700
    Abstract: An FET thin film transistor is formed with a channel formed of a Si/Si.sub.1-x Ge.sub.x /Si three layer sandwich which serves as the carrier transfer channel. The percentage of germanium is preferably less than 30% and should be less than about 50%. The TFT can be structured as top gate, bottom gate or twin gate structure. The Si/Si.sub.1-x Ge/Si sandwich layer is processed in a continuous process under computer control.
    Type: Grant
    Filed: July 26, 1993
    Date of Patent: October 11, 1994
    Assignee: United Microelectronics Corporation
    Inventors: Heng-Sheng Huang, Chun Y. Chang
  • Patent number: 5308780
    Abstract: A method of forming an integrated circuit field effect transistor with surface counter-doped lightly doped drain regions is described. A gate silicon oxide layer is formed on the silicon substrate. A layer of polysilicon is deposited over the gate silicon oxide layer and etched to form a gate electrode structure. A first ion implantation is performed at a tilt angle to form lightly doped drain regions in the semiconductor substrate wherein the lightly doped drain regions are partially overlapped by the gate electrode structure. A second ion implantation is performed at a larger tilt angle and lower energy than the first ion implantation wherein the second ion implantation counter-dopes the surface of the lightly doped drain regions to form a very lightly doped drain layer thus making the lightly doped drain regions buried regions.
    Type: Grant
    Filed: July 22, 1993
    Date of Patent: May 3, 1994
    Assignee: United Microelectronics Corporation
    Inventors: Jih W. Chou, Joe Ko, Chun Y. Chang