Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: An n-type metal oxide semiconductor transistor includes a gate structure, two source/drain regions, two amorphous portions and a silicide. The gate structure is disposed on a substrate. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure, wherein at least one of the source/drain regions is formed with a dislocation. The two amorphous portions are respectively disposed in the two source/drain regions. The silicide is disposed on the two source/drain regions, wherein at least one portion of the silicide overlaps the two amorphous portions.

Abstract: An integrated circuit structure that includes a patterned uppermost conductive layer having a current-carrying trace. The current-carrying trace is connected to an underlying substrate by a multi-layer interconnect structure. The current-carrying trace, which is located around the outer edges of the integrated circuit structure, has at least one edge exhibiting a serpentine pattern. A topside film is located over the patterned uppermost conductive layer, wherein the topside film exhibits an increased thickness adjacent to the serpentine pattern. The increased thickness of the serpentine pattern results in a relatively strong topside film structure near the edges of the substrate. As a result, the portions of the topside film located over inner traces of the uppermost conductive layer are protected from excessive forces during thermal cycling.

Abstract: The present invention uses a clean semiconductor substrate, typically in wafer form, and applies to the surface of the semiconductor a wet chemical that is suspected of containing a contaminant. After drying of the wet chemical, a high temperature, low pressure chemical vapor deposition of a semiconductor material is performed. Metal contaminants that exist on the surface of the semiconductor substrate act as seeds to initiate crystal growth of the semiconductor material that is being deposited. Due to the enhanced crystal growth of the semiconductor material at locations corresponding to positions of the metal contaminant on the semiconductor substrate, a visual inspection of the resulting surface of the semiconductor will indicate the presence of a metal contaminant.

Abstract: A method for forming a via in an integrated circuit having a reduced contact resistance. The integrated circuit includes a photoresist layer, an oxide layer, an etch stop layer and a metal layer. In one embodiment, a portion of the photoresist layer is removed to expose the underlying oxide layer, after which a portion of the oxide layer is removed to expose the underlying etch stop layer. A portion of the etch stop layer is then removed using a reactive ion etch-downstream microwave ash system under conditions that are effective to create a substantially water-soluble polymer residue within the via, to expose a portion of the underlying metal layer. The water-soluble polymer is then removed to expose the underlying metal layer.

Abstract: A spring coil holding device utilizing an integral multi-stage spring coil placed in an actuating sleeve and a housing sleeve, said integral spring coil is actuated to enlarge to a proper caliber by means of said actuating sleeve and housing sleeve for releasing a rod-shaped object or is restored to its original condition by its own resilience for clamp-holding a rod-shaped object.