Abstract: A working platform for an assembly line includes a frame and a guiding mechanism. The frame is mounted over a conveying belt of the assembly line. The frame oppositely has an entry side and an exit side. The guiding mechanism is mounted in the frame. The assembly precision is enhanced by stopping workpieces to be assembled the working platform. Since the workpieces is assembled on the working platform, the assembly labor and cost are reduced.

Abstract: A modular multiplier and an encryption/decryption processor using the modular multiplier, which is mainly applied in a chip to have the needs of small size and faster operation. In the modular multiplier, Montgomery algorithm is realized, the operand is divided into the fixed-length data, and the desired result is provided by the iterative calculation. In the algorithm, two recursive structures include the multiplication operation first and the addition operation later. By the multiplexer to data path's choice, the desired result of modular multiplication can be calculated by a single data path at different time points.

Abstract: Methods and systems for storing texels in memory banks in a manner that allows the retrieval of four neighboring texels within a single cycle are disclosed. The four neighboring texels are stored in separate memory banks according to a predetermined set of combinations of 2-D (u, v) coordinate pairs. In interpolating the color value of a color texel C(u, v), a texel buffer retrieves the four neighboring texels in a single cycle to reduce the memory access time. In one embodiment, a plurality of memory banks in the texel buffer are designed in an interleave mode. In an alternative embodiment, a plurality of memory banks in the texel buffer are implemented in a noninterleave mode. In both embodiments, a texel buffer retrieves the four neighboring texels of a color texel C(u, v) within a single cycle according to a predetermined set of criteria.

Abstract: An address generator is disclosed for performing 2-D virtual coordinate to linear physical memory address conversion. The address generator has an edge walking circuit which receives a 2-D virtual coordinate of a first pixel on a first edge of an object displayed on the display screen. The edge walking circuit selectively outputs a 2-D virtual coordinate of a second pixel which intercepts the first edge of the object at an adjacent pixel row or column to the first pixel. The address generator also has a span expansion circuit which receives the 2-D virtual coordinate of the second pixel. The span expansion circuit selectively expands the 2-D virtual coordinate of the second pixel, according to the number of bits used to represent each pixel and the amount of information which can be accessed at a time from memory. This produces first and second expanded coordinates of the second pixel.