Abstract: A self-moving cleaning device includes: a base; a mobile module adjacent to the base and configured to contact a surface when the self-moving cleaning device moves on the surface; a vacuum module arranged over the base; a dust box arranged over the base and connected to the vacuum module, the dust box including a first opening and a second opening; a first suction port arranged on the base and including a first suction inlet connected to the first opening; a second suction port arranged on the base and including a second suction inlet connected to the second opening, the first suction port disposed between a front side of the base and the second suction port; a roller brush device arranged on the base and within the second suction port; and an air duct, wherein the first suction port is connected to the dust box through the air duct to thereby connect the first suction inlet to the first opening.

Abstract: A self-moving cleaning device includes: a base; a mobile module adjacent to the base and configured to contact a surface when the self-moving cleaning device moves on the surface; a vacuum module arranged over the base; a dust box arranged over the base and connected to the vacuum module, the dust box including a first opening and a second opening; a first suction port arranged on the base and including a first suction inlet connected to the first opening; a second suction port arranged on the base and including a second suction inlet connected to the second opening, the first suction port disposed between a front side of the base and the second suction port; a roller brush device arranged on the base and within the second suction port; and an air duct, wherein the first suction port is connected to the dust box through the air duct to thereby connect the first suction inlet to the first opening.

Abstract: A head-mounted display device includes a belt body, a buckle assembly disposed on the belt body, and an electronic module disposed on the buckle assembly. The buckle assembly includes a base movably fixed to the belt body and a cover detachably disposed on the base. One of the base and the cover includes a sliding rail while the other includes a sliding member. One of the base and the cover includes an arm and a hook protruding from the arm while the other includes an engaging indent. The electronic module including a display module is disposed on the cover. The hook is engaged with the engaging indent so that the cover is fixed to the base.

Abstract: A universal joint module includes a base, a first bearer, a rotor, a fastening member, and an elastic member. The base has an inner space, a hole, and an opening opposite to the hole communicating with the inner space. The first bearer is disposed in the inner space. The rotor includes a knob rotatably disposed in the inner space and leant against the first bearer, and a shaft connected to the knob and passing through the hole. The fastening member is located in the inner space and close to the opening, and movably fastened to the base to adjust a distance between the fastening member and the first bearer. The elastic member located between the first bearer and the fastening member presses the first bearer to preserve a stress between the first bearer and the knob. A head-mounted display device using the universal joint is also provided.

Abstract: A head-mounted display device includes a belt body, a buckle assembly disposed on the belt body, and an electronic module disposed on the buckle assembly. The buckle assembly includes a base movably fixed to the belt body and a cover detachably disposed on the base. One of the base and the cover includes a sliding rail while the other includes a sliding member. One of the base and the cover includes an arm and a hook protruding from the arm while the other includes an engaging indent. The electronic module including a display module is disposed on the cover. The hook is engaged with the engaging indent so that the cover is fixed to the base.

Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.

Abstract: A channel information feedback method adapted in a receiving end of a multiuser multiple input multiple output (MU MIMO) system has following steps. A subspace matrix and a magnitude matrix related to a transmitting end of the MU MIMO system are obtained according to a channel matrix corresponding to the receiving end. A first quantization is performed on the subspace matrix to generate a quantized subspace matrix. A second quantization is performed on an auxiliary information matrix to generate a quantized auxiliary information matrix, where the auxiliary information matrix is corresponding to the magnitude matrix and a residual subspace matrix, and the residual subspace matrix includes residual subspace information after the first quantization is performed on the subspace matrix. The quantized subspace matrix and the quantized auxiliary information matrix are fed back to the transmitting end through an uplink channel.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.

Abstract: An input/output device used for connecting at least one external wire with a display apparatus, comprises a case, at least one I/O connector, a flip cover, and a lighting device. The case embedded in the case of the display apparatus has a wiring slot to provide the wire passing through the case. The I/O connectors embedded on the case are electrically connected to the display apparatus. The flip cover is pivoted on the case. The lighting device having a light source and a switch is associated with the flip cover to turn on or turn off the light source.

Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

Abstract: A channel information feedback method adapted in a receiving end of a multiuser multiple input multiple output (MU MIMO) system has following steps. A subspace matrix and a magnitude matrix related to a transmitting end of the MU MIMO system are obtained according to a channel matrix corresponding to the receiving end. A first quantization is performed on the subspace matrix to generate a quantized subspace matrix. A second quantization is performed on an auxiliary information matrix to generate a quantized auxiliary information matrix, where the auxiliary information matrix is corresponding to the magnitude matrix and a residual subspace matrix, and the residual subspace matrix includes residual subspace information after the first quantization is performed on the subspace matrix. The quantized subspace matrix and the quantized auxiliary information matrix are fed back to the transmitting end through an uplink channel.

Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.

Abstract: A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.

Abstract: A semiconductor device. The semiconductor device includes a substrate having an array region and a decoupling region, a first dielectric layer overlying the substrate, a second dielectric layer overlying the first dielectric layer, a plurality of active components formed in the first dielectric layer within the array region, a first capacitor formed in the second dielectric layer within the array region, a second capacitor formed in the second dielectric layer within the decoupling region, and a first plug formed in the first dielectric layer within the array region electrically connecting the active component and the first capacitor. The invention also provides a method of fabricating the semiconductor device.

Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.

Abstract: A semiconductor device using a recessed step gate. An embodiment comprises a recessed region in a portion of the substrate, a transistor with one source/drain region located within the recessed region and one source/drain region located out of the recessed region, a storage device connected to the source/drain located out of the recessed region, and a bit line connected to the source/drain located within the recessed region.