Abstract: A semiconductor structure includes a first well region disposed within a substrate and comprising a first doping type. A conductive structure overlies the first well region. A pair of first doped regions is disposed within the first well region on opposing sides of the conductive structure. The pair of first doped regions comprise a second doping type opposite the first doping type. A pair of second doped regions is disposed within the first well region on the opposing sides of the conductive structure. The pair of second doped regions comprise the second doping type and are laterally offset from the pair of first doped regions by a non-zero distance.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a transistor, and a capacitor. The transistor includes a gate electrode disposed on the substrate. The capacitor is electrically connected to the transistor and includes a capacitor dielectric and a capacitor electrode. The capacitor dielectric and the capacitor electrode are stacked over the gate electrode of the transistor.

Abstract: A memory device includes a first well region, a second well region, and third well regions. The second well region is interposed between the first region and the third well regions, and the third well regions are separated from one another. The memory device includes floating gates disposed over the first to third well regions, wherein each of the floating gates continuously extends from the first well region to a corresponding one of the third well regions. The memory device includes a bit line write region disposed within the second well region. The bit line write region comprises first source/drain regions on opposite sides of each floating gate. The memory device includes a bit line read region disposed within the second well region and spaced from the bit line write region. The bit line read region comprises second source/drain regions on the opposite sides of each floating gate.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first well region disposed within a substrate and comprising a first doping type. A conductive structure overlies the first well region. A pair of first doped regions is disposed within the first well region on opposing sides of the conductive structure. The pair of first doped regions comprise a second doping type opposite the first doping type. A pair of second doped regions is disposed within the first well region on the opposing sides of the conductive structure. The pair of second doped regions comprise the second doping type and are laterally offset from the pair of first doped regions by a non-zero distance.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region. A second memory active region is disposed within the second well region and is laterally offset from the first memory active region by a non-zero distance.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region.

Abstract: A memory device is disclosed. The memory device includes: a first memory cell, including: a first transistor; a second transistor; and a first capacitor; a second memory cell, including: a third transistor; a fourth transistor; and a second capacitor; a third memory cell, including: a fifth transistor; a sixth transistor; and a third capacitor; and a fourth memory cell, including: a seventh transistor; an eighth transistor; and a fourth capacitor; wherein an electrode of the first capacitor, an electrode of the second capacitor, an electrode of the third capacitor, and an electrode of the fourth capacitor are electrically connected to a conductor. An associated manufacturing method is also disclosed.

Abstract: An integrated chip includes a first well region, second well region, and third well region disposed within a substrate. The second well region is laterally between the first and third well regions. An isolation structure is disposed within the substrate and laterally surrounds the first, second, and third well regions. A floating gate overlies the substrate and laterally extends from the first well region to the third well region. A dielectric structure is disposed under the floating gate. A bit line write region is disposed within the second well region and includes source/drain regions disposed on opposite sides of the floating gate. A bit line read region is disposed within the second well region, is laterally offset from the bit line write region by a non-zero distance, and includes source/drain regions disposed on the opposite sides of the floating gate.

Abstract: A memory device is disclosed. The memory device includes: a first memory cell, including: a first transistor; a second transistor; and a first capacitor; a second memory cell, including: a third transistor; a fourth transistor; and a second capacitor; a third memory cell, including: a fifth transistor; a sixth transistor; and a third capacitor; and a fourth memory cell, including: a seventh transistor; an eighth transistor; and a fourth capacitor; wherein an electrode of the first capacitor, an electrode of the second capacitor, an electrode of the third capacitor, and an electrode of the fourth capacitor are electrically connected to a conductor. An associated manufacturing method is also disclosed.

Abstract: A memory cell may include first and second storage transistors. A first capacitor includes a first capacitor active region disposed within a substrate and a capacitor plate comprised of a first floating gate portion of a floating gate. A second capacitor includes a second capacitor active region disposed within the substrate and a capacitor plate comprised of a second floating gate portion of the floating gate. The first storage transistor includes source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate. The second storage transistor includes source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate. The bit line read and write regions are offset from one another by a non-zero distance.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including first and second storage transistors. A first capacitor includes a first capacitor active region disposed within a substrate and a capacitor plate comprised of a first floating gate portion of a floating gate. A second capacitor includes a second capacitor active region disposed within the substrate and a capacitor plate comprised of a second floating gate portion of the floating gate. The first storage transistor includes source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate. The second storage transistor includes source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate. The bit line read and write regions are offset from one another by a non-zero distance.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first well region, second well region, and third well region disposed within a substrate. The second well region is laterally between the first and third well regions. An isolation structure is disposed within the substrate and laterally surrounds the first, second, and third well regions. A floating gate overlies the substrate and laterally extends from the first well region to the third well region. A dielectric structure is disposed under the floating gate. A bit line write region is disposed within the second well region and comprises source/drain regions disposed on opposite sides of the floating gate. A bit line read region is disposed within the second well region, is laterally offset from the bit line write region by a non-zero distance, and comprises source/drain regions disposed on the opposite sides of the floating gate.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.

Abstract: A memory system is provided. The memory system includes a number of memory cells and a number of bit lines. The memory cells are interlocked with each other in rows and columns. The memory cells include respective capacitors, respective first transistors and respective second transistors. Respective upper plates of the respective capacitors are electrically connected to respective gates of the respective first transistors, and respective drains of the respective second transistors are connected to respective sources of the respective first transistors. The bit lines are arranged along an extending direction of the rows. Respective bit lines are connected to the respective first transistors through respective bit-line contacts, and each of the respective bit-line contacts is shared by two adjacent memory cells of the extending direction of the rows.

Abstract: A memory cell includes a first transistor coupled to a source line, wherein the first transistor is in a first well. The memory cell further includes a second transistor coupled to the first transistor and a bit line, wherein the second transistor is in the first well. The memory cell further includes a first capacitor coupled to a word line and the second transistor, wherein the first capacitor is in a second well. The memory cell further includes a second capacitor coupled to the second transistor and an erase gate, wherein the second capacitor is in the second well. In some embodiments, the first well contacts the second well on a first side of the first well.

Abstract: A memory device is disclosed. The memory device includes: a first memory cell, including: a first transistor; a second transistor; and a first capacitor; a second memory cell, including: a third transistor; a fourth transistor; and a second capacitor; a third memory cell, including: a fifth transistor; a sixth transistor; and a third capacitor; and a fourth memory cell, including: a seventh transistor; an eighth transistor; and a fourth capacitor; wherein an electrode of the first capacitor, an electrode of the second capacitor, an electrode of the third capacitor, and an electrode of the fourth capacitor are electrically connected to a conductor. An associated manufacturing method is also disclosed.

Abstract: A memory cell includes a first transistor coupled to a source line, wherein the first transistor is in a first well. The memory cell further includes a second transistor coupled to the first transistor and a bit line, wherein the second transistor is in the first well. The memory cell further includes a first capacitor coupled to a word line and the second transistor, wherein the first capacitor is in a second well. The memory cell further includes a second capacitor coupled to the second transistor and an erase gate, wherein the second capacitor is in the second well. In some embodiments, the first well contacts the second well on a first side of the first well.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.

Abstract: A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.