Patents by Inventor Chun-Yao Lee

Chun-Yao Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11923360
    Abstract: A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has an U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kun-Yu Lee, Chun-Yao Wang, Chi On Chui
  • Patent number: 10698019
    Abstract: A method is presented to estimate the remaining life of a moving power cable online. The cable is monitored online remotely for further providing suggestions to users for reducing times of power failure and economic loss. An offline AC impedance measurement experiment is designed at first. Three artificial neural networks are established for convert measured impedances into impedances under a baseline context to calculate impedance change ratios. The impedance change ratio indicates the damage of the cable. At last, a remaining margin of the impedance change ratio is figured out online under various contexts with three equations. Thus, the remaining life of the cable is obtained online.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 30, 2020
    Assignee: Chung Yuan Christian University
    Inventors: Ying-Yi Hong, Chun-Yao Lee, Chun-Yi Liu
  • Publication number: 20200158773
    Abstract: A method is presented to estimate the remaining life of a moving power cable online. The cable is monitored online remotely for further providing suggestions to users for reducing times of power failure and economic loss. An offline AC impedance measurement experiment is designed at first. Three artificial neural networks are established for convert measured impedances into impedances under a baseline context to calculate impedance change ratios. The impedance change ratio indicates the damage of the cable. At last, a remaining margin of the impedance change ratio is figured out online under various contexts with three equations. Thus, the remaining life of the cable is obtained online.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Ying-Yi Hong, Chun-Yao Lee, Chun-Yi Liu
  • Publication number: 20160003884
    Abstract: The present invention provides a residual life measuring device for transformer. When using this residual life measuring device to measure a residual life of a transformer, a phase cable of the power transformer is inserted into and passed through a sensing channel of a Hall effect module, and then the phase current of the phase cable is calculated by a process module immediately; meanwhile, the process module is able to further calculate a residual life of the transformer based on the obtained phase current. This residual life measuring device provides a user without having engineering backgrounds to measure the residual life of the power transformer by himself; therefore, according to the measured residual life, the user can determine whether the currently used power transformer needs to be replaced with a new one or not, without completing any complex analysis of the dissolved gas concentration in the insulating oil.
    Type: Application
    Filed: October 12, 2014
    Publication date: January 7, 2016
    Inventor: Chun-Yao Lee
  • Patent number: 8828827
    Abstract: A manufacturing method of an anti punch-through leakage current MOS transistor is provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: September 9, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Chun-Yao Lee, Chin-Lung Chen, Wei-Chun Chang, Hung-Te Lin, Han-Min Huang
  • Patent number: 8692400
    Abstract: A rotating electrical machine abnormal state detection apparatus is provided. The apparatus includes: a current signal acquisition unit, coupled to a rotating electrical machine, for acquiring a set of real-time current waveforms from the rotating electrical machine; a state characteristic database, pre-storing a plurality of abnormal state characteristics which respectively correspond to a plurality of abnormal states; and an abnormal state detection unit, coupled to the current signal acquisition unit and the state characteristic database, for performing signal analysis on the set of real-time current waveforms to produce a current state characteristic, and comparing the current state characteristic with the abnormal state characteristics pre-stored in the state characteristic database to determine the abnormal state of the rotating electrical machine.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: April 8, 2014
    Assignee: Chung Yuan Christian University
    Inventor: Chun-Yao Lee
  • Publication number: 20130344670
    Abstract: A manufacturing method of an anti punch-through leakage current MOS transistor is provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.
    Type: Application
    Filed: August 26, 2013
    Publication date: December 26, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chun-Yao LEE, Chin-Lung Chen, Wei-Chun Chang, Hung-Te Lin, Han-Min Huang
  • Patent number: 8546880
    Abstract: An anti punch-through leakage current MOS transistor and a manufacturing method thereof are provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: October 1, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Yao Lee, Chin-Lung Chen, Wei-Chun Chang, Hung-Te Lin, Han-Min Huang
  • Patent number: 8482063
    Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: July 9, 2013
    Assignee: United Microelectronics Corporation
    Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Wei-Chun Chang, Chun-Yao Lee, Kun-Yi Chou
  • Patent number: 8450801
    Abstract: A lateral-diffusion metal-oxide-semiconductor device includes a semiconductor substrate having at least a field oxide layer, a gate having a layout pattern of a racetrack shape formed on the substrate, a common source formed in the semiconductor substrate and enclosed by the gate, and a drain surrounding the gate and formed in the semiconductor substrate. The gate covers a portion of the field oxide layer. The common source includes a first doped region having a first conductive type and a plurality of islanding second doped regions having a second conductive type. The drain includes a third doped region having the first conductive type. The third doped region overlaps a portion of the field oxide layer and having an overlapping area between the third doped region and the field oxide layer.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: May 28, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Hong-Ze Lin, Bo-Jui Huang, Chin-Lung Chen, Ting-Zhou Yan, Wei-Shan Liao, Han-Min Huang, Chun-Yao Lee, Kun-Yi Chou
  • Publication number: 20130126968
    Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 23, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: An-Hung LIN, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Wei-Chun Chang, Chun-Yao Lee, Kun-Yi Chou
  • Publication number: 20120262131
    Abstract: A rotating electrical machine abnormal state detection apparatus is provided. The apparatus includes: a current signal acquisition unit, coupled to a rotating electrical machine, for acquiring a set of real-time current waveforms from the rotating electrical machine; a state characteristic database, pre-storing a plurality of abnormal state characteristics which respectively correspond to a plurality of abnormal states; and an abnormal state detection unit, coupled to the current signal acquisition unit and the state characteristic database, for performing signal analysis on the set of real-time current waveforms to produce a current state characteristic, and comparing the current state characteristic with the abnormal state characteristics pre-stored in the state characteristic database to determine the abnormal state of the rotating electrical machine.
    Type: Application
    Filed: November 21, 2011
    Publication date: October 18, 2012
    Applicant: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventor: Chun-Yao Lee
  • Publication number: 20120112276
    Abstract: An anti punch-through leakage current MOS transistor and a manufacturing method thereof are provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.
    Type: Application
    Filed: November 10, 2010
    Publication date: May 10, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yao LEE, Chin-Lung Chen, Wei-Chun Chang, Hung-Te Lin, Han-Min Huang
  • Publication number: 20120049277
    Abstract: A lateral-diffusion metal-oxide-semiconductor device includes a semiconductor substrate having at least a field oxide layer, a gate having a layout pattern of a racetrack shape formed on the substrate, a common source formed in the semiconductor substrate and enclosed by the gate, and a drain surrounding the gate and formed in the semiconductor substrate. The gate covers a portion of the field oxide layer. The common source includes a first doped region having a first conductive type and a plurality of islanding second doped regions having a second conductive type. The drain includes a third doped region having the first conductive type. The third doped region overlaps a portion of the field oxide layer and having an overlapping area between the third doped region and the field oxide layer.
    Type: Application
    Filed: August 27, 2010
    Publication date: March 1, 2012
    Inventors: Hong-Ze Lin, Bo-Jui Huang, Chin-Lung Chen, Ting-Zhou Yan, Wei-Shan Liao, Han-Min Huang, Chun-Yao Lee, Kun-Yi Chou