Patents by Inventor Chun-Yau Huang

Chun-Yau Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for electroplating metal wire
    Patent number: 7736483
    Abstract: A method for electroplating low-resistance metal wire for resolving the problem to fabricate the metal wire on large-area substrate through the technology of photolithographing and etching in the prior art. Then the invention improves the RC-delay characteristic of circuit on large-area substrate and reduces the number of masks for processing of a structure of gate overlap lightly-doped drain (source) (GOLDD).
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: June 15, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Yau Huang, Cheng-Chung Chen, Yong-Fu Wu, Cheng-Hung Tsai, Chwan-Gwo Chyau, Fang-Tsun Chu
  • Method for electroplating metal wire
    Publication number: 20070131557
    Abstract: A method for electroplating low-resistance metal wire for resolving the problem to fabricate the metal wire on large-area substrate through the technology of photolithographing and etching in the prior art. Then the invention improves the RC-delay characteristic of circuit on large-area substrate and reduces the number of masks for processing of a structure of gate overlap lightly-doped drain (source) (GOLDD).
    Type: Application
    Filed: January 19, 2007
    Publication date: June 14, 2007
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Yau Huang, Cheng-Chung Chen, Yong-Fu Wu, Cheng-Hung Tsai, Chwan-Gwo Chyau, Fang-Tsun Chu
  • Method for electroplating metal wire
    Publication number: 20040129572
    Abstract: A method for electroplating low-resistance metal wire for resolving the problem to fabricate the metal wire on large-area substrate through the technology of photolithographing and etching in the prior art. Then the invention improves the RC-delay characteristic of circuit on large-area substrate and reduces the number of masks for processing of a structure of gate overlap lightly-doped drain (source) (GOLDD).
    Type: Application
    Filed: August 8, 2003
    Publication date: July 8, 2004
    Applicant: Industrial Technology Research Institute
    Inventors: Chun-Yau Huang, Cheng-Chung Chen, Yong-Fu Wu, Cheng-Hung Tsai, Chwan-Gwo Chyau, Fang-Tsun Chu