Patents by Inventor Chun-Yen Lan
Chun-Yen Lan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230187383Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.Type: ApplicationFiled: February 3, 2023Publication date: June 15, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Wei Lin, Chun-Yen Lan, Tzu-Ting Chou, Tzu-Shiun Sheu, Chih-Wei Lin, Shih-Peng Tai, Wei-Cheng Wu, Ching-Hua Hsieh
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Publication number: 20230067664Abstract: A package structure includes a circuit substrate, a package element and a molding layer. The package element is disposed on the circuit substrate and is electrically connected with the circuit substrate. The molding layer is disposed over the circuit substrate and covers at least a top surface of the circuit substrate. The molding layer includes a first portion wrapping around sidewalls of the package element and having a first thickness, and a second portion surrounding the first portion and connected with the first portion. The first thickness of the first portion is larger than a second thickness of the second portion. A top surface of the first portion of the molding layer is higher than a top surface of the package element.Type: ApplicationFiled: July 15, 2022Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Wei Li, Tzu-Ting Chou, Chun-Yen Lan, Yu-Wei Lin, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Patent number: 11587887Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.Type: GrantFiled: January 14, 2021Date of Patent: February 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Wei Lin, Chun-Yen Lan, Tzu-Ting Chou, Tzu-Shiun Sheu, Chih-Wei Lin, Shih-Peng Tai, Wei-Cheng Wu, Ching-Hua Hsieh
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Publication number: 20220223542Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.Type: ApplicationFiled: January 14, 2021Publication date: July 14, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Wei Lin, Chun-Yen Lan, Tzu-Ting Chou, Tzu-Shiun Sheu, Chih-Wei Lin, Shih-Peng Tai, Wei-Cheng Wu, Ching-Hua Hsieh
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Patent number: 11031376Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.Type: GrantFiled: July 17, 2019Date of Patent: June 8, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsaing-Pin Kuan, Ching-Hua Hsieh, Chih-Wei Lin, Ching-Yao Lin, Chun-Yen Lan, Kai-Ming Chiang
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Publication number: 20210020581Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer.Type: ApplicationFiled: July 17, 2019Publication date: January 21, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsaing-Pin Kuan, Ching-Hua Hsieh, Chih-Wei Lin, Chun-Cheng Lin, Yu-Wei Lin, Chun-Yen Lan
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Publication number: 20210020607Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.Type: ApplicationFiled: July 17, 2019Publication date: January 21, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsaing-Pin Kuan, Ching-Hua Hsieh, Chih-Wei Lin, Ching-Yao Lin, Chun-Yen Lan, Kai-Ming Chiang
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Patent number: 10879192Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer.Type: GrantFiled: July 17, 2019Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsaing-Pin Kuan, Ching-Hua Hsieh, Chih-Wei Lin, Chun-Cheng Lin, Yu-Wei Lin, Chun-Yen Lan