Patents by Inventor Chun-Yi Cheng
Chun-Yi Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250081604Abstract: A method includes following steps. A first transistor is formed on a substrate. A first dielectric layer is formed over the first transistor. A first trench is formed in the first dielectric layer. An amorphous semiconductor layer is deposited in the first trench and over the first dielectric layer. The amorphous semiconductor layer is crystallized into a crystalline semiconductor layer. A second transistor is formed over the crystalline semiconductor layer.Type: ApplicationFiled: September 6, 2023Publication date: March 6, 2025Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., National Yang Ming Chiao Tung UniversityInventors: Yi-Chun LIU, Chun-Yi CHENG, Chien-Te Tu, Chee-Wee LIU
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Publication number: 20240347536Abstract: An integrated circuit includes a first transistor and a second transistor. The first transistor includes first semiconductor channel layers, first gate structure, and a first source structure and a first drain structure on opposites sides of the first gate structure. The second transistor includes second semiconductor channel layers, second gate structure, and a second source structure and a second drain structure on opposites sides of the second gate structure. The first source structure of the first transistor is electrically coupled to the second drain structure of the second transistor. A thickness of each of the first semiconductor channel layers is less than a thickness of each of the second semiconductor channel layers, and a bandgap of a material of the first semiconductor channel layers is larger than a bandgap of a material of the second semiconductor channel layers.Type: ApplicationFiled: April 12, 2023Publication date: October 17, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Hsin-Cheng LIN, Chun-Yi CHENG, Ching-Wang YAO, Chee-Wee LIU
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Publication number: 20240339530Abstract: An integrated circuit includes a first transistor and a second transistor. The first transistor includes first semiconductor channel layers, first gate structure, and a first source structure and a first drain structure on opposites sides of the first gate structure. The second transistor includes second semiconductor channel layers, second gate structure, and a second source structure and a second drain structure on opposites sides of the second gate structure. The first source structure of the first transistor is electrically coupled to the second drain structure of the second transistor. A thickness of each of the first semiconductor channel layers is less than a thickness of each of the second semiconductor channel layers, and a bandgap of a material of the first semiconductor channel layers is larger than a bandgap of a material of the second semiconductor channel layers.Type: ApplicationFiled: April 10, 2023Publication date: October 10, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Hsin-Cheng LIN, Chun-Yi CHENG, Ching-Wang YAO, Chee-Wee LIU
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Patent number: 11655348Abstract: A method for manufacturing a polyimide composite film for a flexible metal-clad substrate includes the following steps, providing a polyamide acid solution; providing fluorine polymer particles and mixing the fluorine polymer particles with a dispersant and an organic solution to prepare a fluorine polymer particle dispersion; forming a colloidal polyimide film from the polyamide acid solution; and coating the colloidal polyimide film with the fluorine polymer particle dispersion and then performing baking to form a polyimide composite film.Type: GrantFiled: June 23, 2021Date of Patent: May 23, 2023Assignee: TAIMIDE TECHNOLOGY INCORPORATIONInventors: Jia-Hao Wu, Chia-Ying Chou, Chun-Yi Cheng
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Publication number: 20230029046Abstract: An IC structure comprises an MTJ cell, a transistor, a first word line, and a second word line. The transistor is electrically coupled to the MTJ cell. The transistor comprises a first gate terminal and a second gate terminal independent of the first gate terminal. The first word line is electrically coupled to the first gate terminal of the transistor. The second word line is electrically coupled to the second gate terminal of the transistor. A resistance state of the MTJ cell is dependent on a first word line voltage applied to the first word line and a second word line voltage applied to the second word line, and the resistance state of the MTJ cell follows an AND gate logic or an OR gate logic.Type: ApplicationFiled: March 8, 2022Publication date: January 26, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chia-Che CHUNG, Chun-Yi CHENG, Chee-Wee LIU
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Publication number: 20220411594Abstract: A method for manufacturing a polyimide composite film for a flexible metal-clad substrate includes the following steps, providing a polyamide acid solution; providing fluorine polymer particles and mixing the fluorine polymer particles with a dispersant and an organic solution to prepare a fluorine polymer particle dispersion; forming a colloidal polyimide film from the polyamide acid solution; and coating the colloidal polyimide film with the fluorine polymer particle dispersion and then performing baking to form a polyimide composite film.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Inventors: JIA-HAO WU, CHIA-YING CHOU, CHUN-YI CHENG
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Patent number: 10886731Abstract: The present application proposes an over-voltage protection circuit for a USB Type-C connector. The USB Type-C connector has at least one input signal pin. The over-voltage protection circuit includes a control circuit, a voltage level shift circuit, and a system clamping circuit. The control circuit generates a control signal according to a bias voltage. The voltage level shift circuit is electrically connected to the at least one input signal pin and the control circuit, and arranged to receive the control signal and at least one input signal and the control signal from the at least one input signal pin, and regulate a voltage level of the at least one input signal according to the control signal. The system clamping circuit is electrically connected to the level shift circuit, and clamps the voltage level of the regulated input signal down to below a threshold.Type: GrantFiled: August 23, 2019Date of Patent: January 5, 2021Assignees: VOLTRON MICROELECTRONICS CORP., UPI SEMICONDUCTOR CORP.Inventor: Chun-Yi Cheng
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Publication number: 20200373756Abstract: The present application proposes an over-voltage protection circuit for a USB Type-C connector. The USB Type-C connector has at least one input signal pin. The over-voltage protection circuit includes a control circuit, a voltage level shift circuit, and a system clamping circuit. The control circuit generates a control signal according to a bias voltage. The voltage level shift circuit is electrically connected to the at least one input signal pin and the control circuit, and arranged to receive the control signal and at least one input signal and the control signal from the at least one input signal pin, and regulate a voltage level of the at least one input signal according to the control signal. The system clamping circuit is electrically connected to the level shift circuit, and clamps the voltage level of the regulated input signal down to below a threshold.Type: ApplicationFiled: August 23, 2019Publication date: November 26, 2020Inventor: CHUN-YI CHENG
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Patent number: 10573587Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, an under bump supporting layer, an attachment layer and solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface and a patterned circuit layer disposed on the first surface, wherein an outer surface of the patterned circuit layer and the first surface are coplanar. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface to encapsulate the chip. The under bump supporting layer is disposed on the first surface and includes openings for exposing the outer surface. The attachment layer covers the inner surface of each opening and the exposed portion of the patterned circuit layer. The solder balls are disposed in the openings respectively and electrically connected to the patterned circuit layer.Type: GrantFiled: August 10, 2017Date of Patent: February 25, 2020Assignee: Industrial Technology Research InstituteInventors: Shu-Wei Kuo, Chun-Yi Cheng, Wei-Yuan Cheng
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Patent number: 10522438Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, a plurality of under ball release layers, and a plurality of solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer includes a plurality of pads protruding from the first surface. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and encapsulates the chip. The under ball release layers cover the pads respectively. The solder balls are disposed on the under ball release layers and electrically connected to the pads.Type: GrantFiled: May 16, 2017Date of Patent: December 31, 2019Assignee: Industrial Technology Research InstituteInventors: Chun-Yi Cheng, Wei-Yuan Cheng, Shu-Wei Kuo, Yu-Jhen Yang
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Publication number: 20190252331Abstract: A high-voltage capacitor structure comprises a capacitor. The capacitor includes a substrate, a field oxidation layer, an active region, a dielectric layer, a passivation layer and a metal layer. The field oxidation layer is disposed above the substrate. The active region is disposed above the substrate or in the substrate. The dielectric layer is disposed above the active region and the field oxidation layer. The passivation layer is disposed above the dielectric layer. The metal layer is disposed above the passivation layer. The metal layer and the active region serve as a first electrode and a second electrode of the capacitor, respectively, wherein the active region is disposed below the dielectric layer. Some embodiments provide a digital isolation apparatus comprising at least one high-voltage isolator, each of which includes the above high-voltage capacitor structure.Type: ApplicationFiled: April 27, 2018Publication date: August 15, 2019Inventor: CHUN-YI CHENG
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Publication number: 20180122732Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, an under bump supporting layer, an attachment layer and solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface and a patterned circuit layer disposed on the first surface, wherein an outer surface of the patterned circuit layer and the first surface are coplanar. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface to encapsulate the chip. The under bump supporting layer is disposed on the first surface and includes openings for exposing the outer surface. The attachment layer covers the inner surface of each opening and the exposed portion of the patterned circuit layer. The solder balls are disposed in the openings respectively and electrically connected to the patterned circuit layer.Type: ApplicationFiled: August 10, 2017Publication date: May 3, 2018Applicant: Industrial Technology Research InstituteInventors: Shu-Wei Kuo, Chun-Yi Cheng, Wei-Yuan Cheng
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Publication number: 20180122694Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, a plurality of under ball release layers, and a plurality of solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer includes a plurality of pads protruding from the first surface. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and encapsulates the chip. The under ball release layers cover the pads respectively. The solder balls are disposed on the under ball release layers and electrically connected to the pads.Type: ApplicationFiled: May 16, 2017Publication date: May 3, 2018Applicant: Industrial Technology Research InstituteInventors: Chun-Yi Cheng, Wei-Yuan Cheng, Shu-Wei Kuo, Yu-Jhen Yang
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Patent number: 7612995Abstract: A shockproof locking assembly device includes a locking hole member, a cavity member, a locking element and a vibration-absorbing element. The cavity member has a bottom portion with a through hole with a recess. The locking element includes a head portion, a shaft portion and a link portion. The head portion is disposed inside the cavity member. The shaft portion penetrates the through hole to be locked into the locking hole member, so that the head portion and the shaft portion are respectively positioned on the top side and the down side of the bottom portion. The link portion has a protrusion with a taper level. The vibration-absorbing element penetrates the through hole, encompasses the link portion and clamps the bottom portion. The shaft portion penetrates through the vibration-absorbing element and the protrusion is locked with the recess via part of the vibration-absorbing element.Type: GrantFiled: February 22, 2006Date of Patent: November 3, 2009Assignee: ASUSTek Computer Inc.Inventor: Chun-Yi Cheng
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Patent number: 7525795Abstract: A hard disk drive holding device includes a holder and at least a sliding trench. A hard disk drive is installed into the device quickly and simply through a sliding trench with an opening on a surface of the holder and is constrained tightly due to an inclination of the lateral inner surface in the sliding trench. The sliding trench may also narrow such that the hard disk drive is also constrained in a different direction and is held firmer.Type: GrantFiled: April 10, 2006Date of Patent: April 28, 2009Assignee: ASUSTek Computer Inc.Inventor: Chun-Yi Cheng
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Publication number: 20070113675Abstract: A circuit board clamping mechanism and a testing device using the same. The circuit board clamping mechanism is for clamping a main circuit board and an extending circuit board. The extending circuit board is coupled with the main circuit board, and there is a titling angel between the extending circuit board and the main circuit board. The circuit board clamping mechanism includes a substrate board and a clamping element. The main circuit board is disposed on the substrate board. The clamping element includes a clamping part and a fixing part. The clamping part is for clamping the extending circuit board. The fixing part is disposed on the substrate board and is coupled with the clamping part. The clamping part and the fixing part form an L-shaped structure.Type: ApplicationFiled: September 28, 2006Publication date: May 24, 2007Applicant: ASUSTek COMPUTER INC.Inventor: Chun-Yi Cheng
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Publication number: 20070072658Abstract: A clam type mobile phone includes a base, a motherboard, a hinge seat, a display device and a vibrator. The motherboard is configured in the base. The hinge seat is mounted on one side of the base. The display device is mounted on the hinge seat. The hinge seat enables the display device to rotate relative to the base. The vibrator is configured in the hinge seat and electrically connected to the motherboard for providing the clam type mobile phone with a vibration function.Type: ApplicationFiled: July 3, 2006Publication date: March 29, 2007Inventor: Chun-Yi Cheng
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Publication number: 20060227502Abstract: A hard disk drive holding device includes a holder and at least a sliding trench. A hard disk drive is installed into the device quickly and simply through a sliding trench with an opening on a surface of the holder and is constrained tightly due to an inclination of the lateral inner surface in the sliding trench. The sliding trench may also narrow such that the hard disk drive is also constrained in a different direction and is held firmer.Type: ApplicationFiled: April 10, 2006Publication date: October 12, 2006Inventor: Chun-Yi Cheng
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Publication number: 20060202100Abstract: A shockproof locking assembly device includes a locking hole member, a cavity member, a locking element and a vibration-absorbing element. The cavity member has a bottom portion with a through hole with a recess. The locking element includes a head portion, a shaft portion and a link portion. The head portion is disposed inside the cavity member. The shaft portion penetrates the through hole to be locked into the locking hole member, so that the head portion and the shaft portion are respectively positioned on the top side and the down side of the bottom portion. The link portion has a protrusion with a taper level. The vibration-absorbing element penetrates the through hole, encompasses the link portion and clamps the bottom portion. The shaft portion penetrates through the vibration-absorbing element and the protrusion is locked with the recess via part of the vibration-absorbing element.Type: ApplicationFiled: February 22, 2006Publication date: September 14, 2006Inventor: Chun-Yi Cheng
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Publication number: 20060157904Abstract: An apparatus for fixing a workpiece by a magnetic force includes a carrier and a fixing unit. The carrier is made of a magnetic material. The fixing unit is disposed on the workpiece, fixing the workpiece on the carrier. The fixing unit includes a supporting portion, a magnet and a connecting portion. The magnet is disposed in the supporting portion. The connecting portion is connected to the supporting portion and is used for being joined to the workpiece. The fixing unit is fixed on the carrier by a magnetic force, for fixing the workpiece on the carrier.Type: ApplicationFiled: January 18, 2006Publication date: July 20, 2006Inventors: Yu-Chi Li, Kyi-Lyan Lee, Chun-Yi Cheng