Patents by Inventor Chun-Yi Chou

Chun-Yi Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151372
    Abstract: A method includes forming first semiconductive sheets over a substrate and arranged in a vertical direction, and second semiconductive sheets over the substrate and arranged in the vertical direction, wherein a number of the second semiconductive sheets is different than a number of the first semiconductive sheets; forming first source/drain regions on either side of each of the first semiconductive sheets, and second source/drain regions on either side of each of the second semiconductive sheets; forming a first gate around each of the first semiconductive sheets, and a second gate around each of the second semiconductive sheets.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Yi CHOU, Guan-Lin CHEN, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250113539
    Abstract: A method includes forming semiconductive sheets over a substrate and arranged in a vertical direction; forming source/drain regions on either side of each of the semiconductive sheets; forming first air gap inner spacers interleaving with the semiconductive sheets; forming a gate around each of the semiconductive sheets, wherein the first air gap inner spacers are laterally between the gate and a first one of the source/drain regions.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Yi CHOU, Guan-Lin CHEN, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250087482
    Abstract: A device includes gate spacers, a gate dielectric layer, and one or more gate metals. The gate spacers are over a substrate. The gate dielectric layer is between the gate spacers. The gate dielectric layer includes a horizontal portion extending parallel to a top surface of the substrate, and vertical portions extending upwards from the horizontal portion. A first one of the vertical portions has a thickness less than a thickness of the horizontal portion.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Chun-Yi CHOU, Po-Hsien CHENG, Tse-An CHEN, Miin-Jang CHEN
  • Publication number: 20250072052
    Abstract: A device includes a transistor. The transistor includes a plurality of stacked channels, a source/drain region coupled to the stacked channels, and a gate metal wrapped around the stacked channels. The transistor includes a plurality of inner spacers, each inner spacer being positioned laterally between the gate metal and the source/drain region and including a gap and an inner spacer liner layer between the gate metal and the source/drain region.
    Type: Application
    Filed: January 11, 2024
    Publication date: February 27, 2025
    Inventors: Chun Yi CHOU, Guan-Lin CHEN, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 12191144
    Abstract: A method includes forming a mask layer above a substrate. The substrate is patterned by using the mask layer as a mask to form a trench in the substrate. An isolation structure is formed in the trench, including feeding first precursors to the substrate. A bias is applied to the substrate after feeding the first precursors. With the bias turned on, second precursors are fed to the substrate. Feeding the first precursors, applying the bias, and feeding the second precursors are repeated.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: January 7, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Chun-Yi Chou, Po-Hsien Cheng, Tse-An Chen, Miin-Jang Chen
  • Patent number: 12033850
    Abstract: A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: July 9, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Chun-Yi Chou, Po-Hsien Cheng, Tse-An Chen, Miin-Jang Chen
  • Publication number: 20240102162
    Abstract: A method includes following steps. A first precursor is pulsed over a substrate such that first precursor adsorbs on a first region and a second region of the substrate. A first plurality of the first precursor adsorbing on the first region is then removed using a plasma, while leaving a second plurality of the first precursor adsorbing on the second region. A second precursor is then pulsed to the substrate to form a monolayer of a film on the second region and a material on the first region. The material is then removed using a plasma. The substrate is biased during removing the material.
    Type: Application
    Filed: February 1, 2023
    Publication date: March 28, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chun-Yi CHOU, Chih-Piao CHUU, Miin-Jang CHEN
  • Publication number: 20230115597
    Abstract: A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 13, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chun-Yi CHOU, Po-Hsien CHENG, Tse-An CHEN, Miin-Jang CHEN
  • Publication number: 20220375782
    Abstract: A method includes forming a mask layer above a substrate. The substrate is patterned by using the mask layer as a mask to form a trench in the substrate. An isolation structure is formed in the trench, including feeding first precursors to the substrate. A bias is applied to the substrate after feeding the first precursors. With the bias turned on, second precursors are fed to the substrate. Feeding the first precursors, applying the bias, and feeding the second precursors are repeated.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 24, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chun-Yi CHOU, Po-Hsien CHENG, Tse-An CHEN, Miin-Jang CHEN
  • Patent number: 11508572
    Abstract: A method includes forming a dummy gate structure over a wafer. Gate spacers are formed on either side of the dummy gate structure. The dummy gate structure is removed to form a gate trench between the gate spacers. A gate dielectric layer is formed in the gate trench. A gate electrode is formed over the gate dielectric layer. Forming the gate dielectric layer includes applying a first bias to the wafer. With the first bias turned on, first precursors are fed to the wafer. The first bias is turned off. After turning off the first bias, second precursors are fed to the wafer.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: November 22, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chun-Yi Chou, Po-Hsien Cheng, Tse-An Chen, Miin-Jang Chen
  • Patent number: 11383195
    Abstract: A device for capturing particles includes a gas-guiding unit, a gas-guiding unit and a mist-elimination unit. The gas-guiding unit has opposing first and second ends. The mist-elimination unit is disposed at the second end. The liquid-circulation unit, disposed under the mist-elimination unit by surrounding the gas-guiding unit, includes through holes below the gas-guiding unit by a gap. A gas containing particles enters the channel via the first end and then the mist-elimination unit via the second end. While the gas flows into the channel, the liquid in the liquid-circulation unit is inhaled into the channel via the gap to form droplets containing particles. After the droplets are captured by the mist-elimination unit, the liquid formed at the mist-elimination unit flows down into the liquid-circulation unit to reform the liquid to be further inhaled back to the channel of the gas-guiding unit via the gap.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: July 12, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tsung-Jen Ho, Sheng-Fu Huang, Yen-Chun Liu, Chun-Yi Chou
  • Patent number: 11340738
    Abstract: A method for force sensing using information from a display panel with a touch sensor and a fingerprint sensor is introduced. The method includes: obtaining, based on touch sensing data from a touch sensing circuit coupled to the touch sensor, first sensing information indicating capacitance value distribution over a touch sensing area due to pressing of an object on the display panel; obtaining, based on fingerprint sensing data from a fingerprint sensing circuit coupled to the fingerprint sensor, second sensing information indicating an effective pressing area due to the pressing of the object; and generating third sensing information indicating a force corresponding to the pressing of the object, based on the first sensing information and the second sensing information. An electronic module capable of facilitating force sensing and computing apparatus capable of force sensing are also provided.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: May 24, 2022
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventor: Chun-Yi Chou
  • Publication number: 20220057871
    Abstract: A method for force sensing using information from a display panel with a touch sensor and a fingerprint sensor is introduced. The method includes: obtaining, based on touch sensing data from a touch sensing circuit coupled to the touch sensor, first sensing information indicating capacitance value distribution over a touch sensing area due to pressing of an object on the display panel; obtaining, based on fingerprint sensing data from a fingerprint sensing circuit coupled to the fingerprint sensor, second sensing information indicating an effective pressing area due to the pressing of the object; and generating third sensing information indicating a force corresponding to the pressing of the object, based on the first sensing information and the second sensing information. An electronic module capable of facilitating force sensing and computing apparatus capable of force sensing are also provided.
    Type: Application
    Filed: August 18, 2020
    Publication date: February 24, 2022
    Inventor: Chun-Yi Chou
  • Publication number: 20210313168
    Abstract: A method includes forming a dummy gate structure over a wafer. Gate spacers are formed on either side of the dummy gate structure. The dummy gate structure is removed to form a gate trench between the gate spacers. A gate dielectric layer is formed in the gate trench. A gate electrode is formed over the gate dielectric layer. Forming the gate dielectric layer includes applying a first bias to the wafer. With the first bias turned on, first precursors are fed to the wafer. The first bias is turned off. After turning off the first bias, second precursors are fed to the wafer.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chun-Yi CHOU, Po-Hsien CHENG, Tse-An CHEN, Miin-Jang CHEN
  • Patent number: 11120722
    Abstract: A data transmission method applied in a display, which includes a display panel, is provided. The data transmission method includes the following steps of: providing a host controller and n display drivers, n is a natural number greater than 1; providing a communication link under mobile industry processor interface (MIPI), connecting the host controller to the n display drivers; determining n virtual channel values Vc1-Vcn corresponding to the respective n display drivers; employing the host controller for providing a command with a virtual channel parameter through the communication link under MIPI; when the virtual channel parameter corresponds to an ith virtual channel values Vci, an ith display driver executing corresponding operations in response to the command, while the rest n?1 display drivers ignoring the command, wherein i is a natural number smaller than or equal to n.
    Type: Grant
    Filed: October 27, 2019
    Date of Patent: September 14, 2021
    Assignee: Novatek Microelectronics Corp.
    Inventors: Po-Chuan Chang-Chian, Chun-Yi Chou, Wing-Kai Tang, Ching-Chun Lin, Chih-Wei Tang
  • Publication number: 20210154616
    Abstract: A device for capturing particles includes a gas-guiding unit, a gas-guiding unit and a mist-elimination unit. The gas-guiding unit has opposing first and second ends. The mist-elimination unit is disposed at the second end. The liquid-circulation unit, disposed under the mist-elimination unit by surrounding the gas-guiding unit, includes through holes below the gas-guiding unit by a gap. A gas containing particles enters the channel via the first end and then the mist-elimination unit via the second end. While the gas flows into the channel, the liquid in the liquid-circulation unit is inhaled into the channel via the gap to form droplets containing particles. After the droplets are captured by the mist-elimination unit, the liquid formed at the mist-elimination unit flows down into the liquid-circulation unit to reform the liquid to be further inhaled back to the channel of the gas-guiding unit via the gap.
    Type: Application
    Filed: June 18, 2020
    Publication date: May 27, 2021
    Inventors: TSUNG-JEN HO, SHENG-FU HUANG, YEN-CHUN LIU, CHUN-YI CHOU
  • Publication number: 20210065627
    Abstract: The present invention provides a control method for a touch and organic light-emitting diode (OLED) driver, for controlling an OLED touch panel. The OLED touch panel has a dark screen mode and a normal display mode, and includes a cathode layer of OLEDs. The control method includes a plurality of steps, and the steps include applying a first load-free driving (LFD) signal to the cathode layer or controlling the cathode layer to be floating during a touch sensing period in the dark screen mode; and applying a constant voltage to the cathode layer in the normal display mode.
    Type: Application
    Filed: May 24, 2020
    Publication date: March 4, 2021
    Inventor: Chun-Yi Chou
  • Publication number: 20200058244
    Abstract: A data transmission method applied in a display, which includes a display panel, is provided. The data transmission method includes the following steps of: providing a host controller and n display drivers, n is a natural number greater than 1; providing a communication link under mobile industry processor interface (MIPI), connecting the host controller to the n display drivers; determining n virtual channel values Vc1-Vcn corresponding to the respective n display drivers; employing the host controller for providing a command with a virtual channel parameter through the communication link under MIPI; when the virtual channel parameter corresponds to an ith virtual channel values Vci, an ith display driver executing corresponding operations in response to the command, while the rest n?1 display drivers ignoring the command, wherein i is a natural number smaller than or equal to n.
    Type: Application
    Filed: October 27, 2019
    Publication date: February 20, 2020
    Applicant: Novatek Microelectronics Corp.
    Inventors: Po-Chuan Chang-Chian, Chun-Yi Chou, Wing-Kai Tang, Ching-Chun Lin, Chih-Wei Tang
  • Patent number: 10515576
    Abstract: A data transmission method applied in a display, which includes a display panel, is provided. The data transmission method includes the following steps of: providing a host controller and n display drivers, n is a natural number greater than 1; providing a communication link under mobile industry processor interface (MIPI), connecting the host controller to the n display drivers; determining n virtual channel values Vc1-Vcn corresponding to the respective n display drivers; employing the host controller for providing a command with a virtual channel parameter through the communication link under MIPI; when the virtual channel parameter corresponds to an ith virtual channel values Vci, an ith display driver executing corresponding operations in response to the command, while the rest n?1 display drivers ignoring the command, wherein i is a natural number smaller than or equal to n.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: December 24, 2019
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Po-Chuan Chang-Chian, Chun-Yi Chou, Wing-Kai Tang, Ching-Chun Lin, Chih-Wei Tang
  • Patent number: 9825388
    Abstract: A layout method applied to a connector is provided. The connector is electrically connected between a flexible printed circuit (FPC) and a printed circuit board (PCB). The FPC includes M pairs of differential lines and X shield lines. The PCB includes M pairs of differential lines and Z shield lines. The layout method includes following steps. Firstly, M pairs of conductive lines are disposed on the connector. The M conductive lines are correspondingly electrically connected to the M differential lines of the FPC and the M differential lines of the PCB. Then; Y conductive lines are disposed on the connector, wherein Y is smaller than X. Furthermore, at least one of the Y conductive lines is electrically connected to at least one of the X shield lines and at least one of the Z shield lines.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: November 21, 2017
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chun-Yi Chou, Yu-Chang Pai, Teng-Yang Tan, Shih-Wei Tseng