Abstract: A chip includes one or more function input pads, a sequence generation circuit, one or more logic circuits, one or more scan chains, a selection circuit, and one or more sequence output pads. The function input pad is configured to receive a function sequence. The sequence generation circuit is configured to generate a diagnosis sequence. The logic circuit includes a plurality of logic gates, for responding to the function sequence and outputting one or more logic results. When enabled by the selection circuit, the scan chain outputs a response result in response to the logic result or a diagnosis result in response to the diagnosis sequence. The sequence output pad receives the diagnosis result when the scan chain responds to the diagnosis sequence.

Abstract: The present invention discloses a test device for testing an integrated circuit. An embodiment of the test device includes an on-chip-clock controller (OCC), a pulse debugging circuit and a register circuit. The OCC is configured to generate an output clock according to an input clock, in which the output clock is for testing a circuitry under test (CUT) that is included in the test device. The pulse debugging circuit is configured to generate a pulse record according to a pulse number of the output clock, in which the pulse record is used to find out whether a test status dependent upon the output clock is abnormal. The register circuit is configured to store and output the pulse record according to a reliable clock.

Abstract: A portable gas detecting device includes at least one detecting chamber, at least one gas sensor and at least one actuator. The gas sensor is disposed in the detecting chamber and configured for monitoring gas inside the detecting chamber. The actuator is disposed in the detecting chamber and includes a piezoelectric actuator. When an actuating signal is applied to the piezoelectric actuator and the piezoelectric actuator generates a resonance effect, the gas outside the detecting chamber is introduced into the detecting chamber for sampling. The actuator is driven by an instantaneous sampling pulse to control a trace of gas to flow into the detecting chamber for forming a stable airflow environment. In the stable airflow environment, a gas molecule is dissolved in or bonded to a reaction material on a surface of the gas sensor for reacting.

Abstract: An antenna module is disclosed. The antenna module includes a circuit board and at least one antenna set. Wherein, the antenna set includes a driving antenna and a plurality of parasitic antennas. The driving antenna is formed on the circuit board, and the parasitic antennas are positioned with the driving antenna as a center on the circuit board. Whereby, the space occupied by the antenna module can be small, and beams of wireless signals radiated by the antenna module can be controlled.

Abstract: A miniature transportation device is disclosed and includes a gas inlet plate, a resonance plate and a piezoelectric actuator, which are stacked on each other sequentially. The gas inlet plate comprises at least one inlet, at least one convergence channel and a convergence chamber. The convergence channel is in fluid communication with the inlet and the convergence channel. The resonance plate comprises a central aperture. A chamber gap is formed between the resonance plate and the piezoelectric actuator to define a first chamber. When the piezoelectric actuator is enabled, the gas is fed into the miniature gas transportation device through the inlet of the gas inlet plate, converged to the convergence chamber through the convergence channel, transferred through the central aperture of the resonance plate, introduced into the first chamber, and transferred along a transportation direction through a vacant space of the piezoelectric actuator to be discharged continuously.

Abstract: An actuating and sensing module includes a first substrate, a second substrate, an actuating device and a sensor. The first and second substrates are stacked on each other as a gas flow channel is formed therebetween. The gas inlet, the gas flow channel and the gas outlet are in communication with each other to define a gas flow path. The actuating device is disposed in the gas outlet of the second substrate and electrically connected to a control circuit to obtain driving power. The sensor is disposed in the gas flow path and misaligned with the gas inlet. The sensor is spaced apart from the actuating device and is electrically connected to the control circuit. Being driven by the actuating device, the gas is transported from the outside into the gas flow path and monitored by the sensor.

Abstract: An electronic device includes a controller, a user interface and a sensor. The user interface and the sensor are coupled to the controller. The user interface is configured to send a first user command to the controller to control the controller to enter a burst mode. The controller is configured to control the sensor to continuously sense a chip or an environment where the chip is located to generate multiple sensing values, and to generate a sensing data according to the sensing values after the controller receives the first user command to enter the burst mode.

Abstract: A gas detecting device includes an actuating-and-sensing module, a driving controller, a data storage device and a data processor. The actuating-and-sensing module includes a first gas sensor, a second gas sensor and a gas transportation actuator. The driving controller controls the actuations and non-actuations of the first gas sensor, the second gas sensor and the gas transportation actuator. The first gas sensor measures the target gas and transmits first gas measured information to the data storage device. The second gas sensor measures the target gas and transmits second gas measured information to the data storage device. The data processor calculates concentrations of the gases in the target gas by comparing the information stored in a gas database, the first gas measured information and the second gas measured information.

Abstract: The present invention discloses a test device for testing an integrated circuit. An embodiment of the test device includes an on-chip-clock controller (OCC), a pulse debugging circuit and a register circuit. The OCC is configured to generate an output clock according to an input clock, in which the output clock is for testing a circuitry under test (CUT) that is included in the test device. The pulse debugging circuit is configured to generate a pulse record according to a pulse number of the output clock, in which the pulse record is used to find out whether a test status dependent upon the output clock is abnormal. The register circuit is configured to store and output the pulse record according to a reliable clock.

Abstract: A process for producing ethylene from an ethanol feedstock comprises a step of subjecting the ethanol feedstock to a dehydration reaction in the presence of a supported heteropolyacid salt catalyst. The supported heteropolyacid salt catalyst includes a support and a heteropolyacid salt compound which is carried on the support and which is represented by a formula as defined herein.

Abstract: A circuit debugging method includes: utilizing a debugging circuit to determine an operating status of a specific circuit to generate a result; utilizing a register located in a scan chain path to store the result, wherein the scan chain path is arranged for a scan test; and utilizing an output pad located in the scan chain path to output the result, wherein the result is arranged to be indicative of the operating status of the specific circuit.

Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

Abstract: An antenna module is disclosed. The antenna module includes a circuit board and at least one antenna set. Wherein, the antenna set includes a driving antenna and a plurality of parasitic antennas. The driving antenna is formed on the circuit board, and the parasitic antennas are positioned with the driving antenna as a center on the circuit board. Whereby, the space occupied by the antenna module can be small, and beams of wireless signals radiated by the antenna module can be controlled.

Abstract: An electronic device includes a controller, a user interface and a sensor. The user interface and the sensor are coupled to the controller. The user interface is configured to send a first user command to the controller to control the controller to enter a burst mode. The controller is configured to control the sensor to continuously sense a chip or an environment where the chip is located to generate multiple sensing values, and to generate a sensing data according to the sensing values after the controller receives the first user command to enter the burst mode.

Abstract: A photosensitive composition is provided. The photosensitive composition includes a composition for forming polyimide, a photoinitiator, a photo cross-linking agent, and a thermal cross-linking agent. The composition for forming polyimide includes a diamine monomer component, an anhydride monomer component, and a polyimide modifier. The diamine monomer component includes a long-chain aliphatic diamine monomer, a carboxylic acid-containing diamine monomer, and a triazole compound. The anhydride monomer component includes a dianhydride monomer and a monoanhydride monomer. The polyimide modifier has a double bond and an epoxy group.

Abstract: A multiple defect diagnosis method includes: receiving a gate-level netlist of a chip, a plurality of test patterns and a plurality of test failure reports; deriving a plurality of seed nets from the gate-level netlist according to the plurality of test patterns and the plurality of test failure reports; utilizing a processor to compute similarity between the plurality of seed nets, and accordingly merging the plurality of seed nets to obtain a single seed net tree; and deriving at least one suspected seed net according to the single seed net tree.

Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

Abstract: A voltage and frequency scaling apparatus includes a processor, at least one sensor and a controller. The at least one sensor is electrically coupled to the processor. The at least one sensor measures at least one device characteristic of at least one logic circuit of a system on chip, and transmits at least one sensing result to the processor. The processor generates a control signal according to the at least one sensing result. The controller receives the control signal and adjusts at least one of the operating frequency and the operating voltage of at least one logic circuit. Furthermore, a system on chip (SoC) and a voltage and frequency scaling method are also described herein.

Abstract: An integrated circuit includes a Built-In Self-Test (BIST) circuit, a predetermined signature pattern and a Read Only Memory (ROM), wherein the predetermined signature pattern is stored in the integrated circuit. The ROM stores at least effective information and a BIST signature adjustment code, the BIST signature adjustment code is irrelevant to any functional information stored in the ROM; wherein the BIST circuit is used to test content stored in the ROM to generate a signature pattern, and compare the signature pattern with the predetermined signature pattern to judge if the content stored in the ROM has error.