Abstract: The present invention relates to a heat radiating structure in all-in-one computers, comprising a pedestal, mainframe module and back cover. The mainframe module is contained in a containing stand behind the pedestal, and a motherboard is included in the containing space in front of a mainframe module base. The motherboard's CPU sticks through a radiator to a heat radiating aluminum plate in the rear of the containing space, while the hard disk drive is close to the heat radiating aluminum plate, and the pedestal is covered by the back cover on the back. With the heat radiating aluminum plate to quickly conduct heat and its multiple heat radiating holes, heat dispersing holes behind the containing stand and hollowed grooves on the back cover to convect hot air.

Abstract: A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.

Abstract: Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.

Abstract: An electronic device including a bio-polymer material and a method for manufacturing the same are disclosed. The electronic device of the present invention comprises: a substrate; a first electrode disposed on the substrate; a bio-polymer layer disposed on the first electrode, wherein the bio-polymeric material is selected from a group consisting of wool keratin, collagen hydrolysate, gelatin, whey protein and hydroxypropyl methylcellulose; and a second electrode disposed on the biopolymer material layer. The present invention is suitable for various electronic devices such as an organic thin film transistor, an organic floating gate memory, or a metal-insulator-metal capacitor.

Abstract: The present invention relates to a heat radiating structure in all-in-one computers, comprising a pedestal, mainframe module and back cover. The mainframe module is contained in a containing stand behind the pedestal, and a motherboard is included in the containing space in front of a mainframe module base. The motherboard's CPU sticks through a radiator to a heat radiating aluminum plate in the rear of the containing space, while the hard disk drive is close to the heat radiating aluminum plate, and the pedestal is covered by the back cover on the back. With the heat radiating aluminum plate to quickly conduct heat and its multiple heat radiating holes, heat dispersing holes behind the containing stand and hollowed grooves on the back cover to convect hot air.

Abstract: A circuit board and a method for manufacturing the same are disclosed. The circuit board of the present invention comprises: a carrier board, wherein a first circuit layer is disposed on at least one surface of the carrier board, and the first circuit layer comprises plural conductive pads; a protein dielectric layer disposed on the surface of the carrier board and the first circuit layer, wherein the protein dielectric layer has plural openings to expose the conductive pads; and a second circuit layer disposed on a surface of the protein dielectric layer, wherein the second circuit layer comprises plural first conductive vias, and each first conductive via is correspondingly formed in the opening and electrically connects to the conductive pad.

Abstract: A method for fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features in an inter-layer dielectric (ILD) over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. Source/drain (S/D) features are formed at edges of the active gate features in the substrate for forming transistor devices. The disclosed method provides an improved method for reducing parasitic capacitance among the transistor devices. In an embodiment, the improved formation method is achieved by introducing species into the dummy gate feature to increase the resistance of the dummy gate feature.

Abstract: A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a first operational voltage for receiving a first control signal. The first word line comprises a start terminal connected to an output terminal of the first word line driver. The first switch is connected to a second operational voltage and an end terminal of the first word line. The second operational voltage is not smaller than the first operational voltage. When the first word line driver is controlled by the first control signal to start charging up the first word line, the first switch is simultaneously turned on to provide another charging path for the first word line until the first word line is charged to the first operational voltage.

Abstract: Provided is a method and structure for utilizing advance channel substrate materials in semiconductor manufacturing. Advanced channel substrate materials such as germanium and Group III-V channel substrate materials, are advantageously utilized. One or more capping films including at least a nitride layer are formed over the channel substrate prior to patterning, ion implantation and the subsequent stripping and wet cleaning operations. With the capping layers intact during these operations, attack of the channel substrate material is prevented and the protective films are easily removed subsequently. The films are dimensioned in conjunction with the ion implantation operation to enable the desired dopant profile and concentration to be formed in the channel substrate material.

Abstract: A heat sink assembly includes a fin module, heat pipes, and a pair of side plates. The fin module is composed of a plurality of fins and has a flat side formed with a trough and two recesses. Each of the heat pipes has an evaporation section. The evaporation sections are parallelly accommodated in the trough and in contact with each other. The side plates are separately fixed in the recesses and protrude from the flat side. The evaporation sections are formed with a flat surface coplanar with the side plates. By this arrangement, the thermal contact area between the heat pipes and a heat source is increased to thereby improve the heat-dissipating efficiency of the heat sink assembly.

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract: The present invention relates to a heat sink having juxtaposed heat pipes and a method for manufacturing the same. The heat sink includes a base, a plurality of heat pipes and a pair of side strips. The base has a surface on which an open trough and an insertion trough on both sides of the open trough are provided. Each heat pipe has an evaporating section. The evaporating sections are juxtaposed in the open trough and adhered to each other. Each evaporating section has a planar surface. The side strips are fixed into the insertion troughs and protrude from the surface of the base. The planar surface of each evaporating section and the outer surface of each side strip are coplanar. By this structure, the thermal contact surface between the heat pipes and electronic heat-generating sources is increased, so that the heat-dissipating efficiency of the heat sink is improved.

Abstract: A method for testing a digital camera module reads a digital image from the digital camera module under test, extracts a tricolor coefficient of each pixel of the digital image to form a measurement array, and compares the measurement array with a reference array to find tricolor coefficient differences. The method extracts an edge of the digital image, processes the edge of the digital image using binarization to obtain measurement binary values, and compares the measurement binary values with reference binary values to find binary values differences. The method further compares a count of the tricolor coefficient differences with a first acceptable value, and compares a count of the binary values differences with a second acceptable value to determine quality of the digital camera module.

Abstract: An N-type organic thin film transistor, an ambipolar field-effect transistor, and methods of fabricating the same are disclosed. The N-type organic thin film transistor of the present invention comprises: a substrate; a gate electrode locating on the substrate; a gate-insulating layer covering the gate electrode, and the gate-insulating layer is made of silk protein; a buffering layer locating on the gate-insulating layer, and the buffering layer is made of pentacene; an N-type organic semiconductor layer locating on the buffering layer; and a source and a drain electrode, wherein the N-type organic semiconductor layer, the buffering layer, the source and the drain electrode are disposed over the gate dielectric layer.

Abstract: A liquid crystal composite material and a liquid crystal electro-optical display device are provided. A liquid crystal composite material, includes: a liquid crystal; a polymer; and a modified inorganic layered material, wherein the modified inorganic layered material is formed by modifying an inorganic layered material with a conjugated oligomer, and the conjugated oligomer has a quaternary ammonium group or sulfonate group.

Abstract: A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.

Abstract: A memory device comprises a memory array, a status register, a status-register write-protect bit and a security register. The memory array contains a number of memory blocks. The status register includes at least one protection bit indicative of a protection status of at least one corresponding block of the memory blocks. The status-register write-protect bit is coupled with the status register for preventing a state change of the at least one protection bit. The security register includes at least one register-protection bit for preventing the state change in one of the at least one protection bit of the status register and the status-register write-protect bit.

Abstract: An improved solar cell module and a method of manufacturing the same are disclosed in the invention. The solar cell modules includes: a solar cell matrix, having a number of conductive wires, for transforming solar energy into electric energy to be outputted; a front sheet, formed on one side of the solar cell matrix, for passing solar light; a back sheet, formed on the other side of the solar cell matrix, for passing solar light; and an isolating cover, covering the solar cell matrix, for protecting the solar cell matrix from stress, humidity and heat. A number of holes are formed through the back sheet and the isolating cover, the conductive wires are soldered with insulated cables passing through the holes, and an adhesive is used to seal the hole and fix the cables.

Abstract: A rectangular protective frame for a solar cell module is disclosed. The rectangular protective frame for a solar cell module includes: four bar elements, each including: a supporting portion, having an L-shape cross-section, encompassing edges of the solar cell module for supporting the solar cell module; and a body portion, having a rectangular cross-section with a long side connected to the supporting portion for increasing strength of the supporting portion. The rectangular protective frame also includes at least one carrying mechanism, connected to a short side of the body portion of at least one of the four bar elements, having an L-shape cross-section, for preventing fingers from slipping off while carrying the rectangular protective frame.

Abstract: In an embodiment, an oligoaniline exfoliating agent, as shown in Formula (I), is provided. In Formula (I), R is —H or —NH2, and n is 3 to 30. In another embodiment, exfoliated platelet-shaped clay including the oligoaniline exfoliating agent and a method for preparing the exfoliated platelet-shaped clay are provided.