Abstract: A mobile computing device configured to manage a digital wallet card within a mobile wallet on the device by communicating with a central server. The mobile computing device continually communicates with the central server that stores policy information for an account associated with the digital wallet card. If the central server detects an update to the digital wallet card then, based on such indication, the mobile computing device generates an alert such as a notification to be displayed on a user interface of the mobile computing device indicating the existence of the update. The mobile computing device displays concurrently the notification of an update and an embedded link that when selected triggers downloading the update and replacing the digital wallet card with an updated digital wallet card in the mobile wallet.

Abstract: A computer-implemented method may include: receiving, from a first electronic device during an unauthenticated session, a request for provisioning data, the request associated with identification data insufficient to begin an authenticated session; determining, based on the identification data, whether the request for the provisioning data is associated with an existing account; when the request for the provisioning data is determined to be associated with an existing account, obtaining the provisioning data based on a modifier not available if the request for the provisioning data is not determined to be associated with an existing account; and sending the provisioning data to the first electronic device.

Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.

Abstract: A technology for calibrating device-end operational information of a data storage system is shown. A controller operates a non-volatile memory with reference to operational information. A second type of logical address requested by the host that is different from the first type of logical address used in operating a file system of a host is introduced. As indicated by the second type of logical address, the controller receives calibration information from the host and calibrates the operational information based on the calibration information.

Abstract: The present disclosure illustrates a method and an apparatus of fiber tracking, and non-transitory computer-readable medium thereof. In an embodiment, a fiber tracking process is performed on a diffusion magnetic resonance image of a subject's brain based on validated and better tracking parameters, so as to obtain first tracking images, nerve fibers between two first regions of interest in each of the first tracking images are extracted, a nerve fasciculus skeleton is established based on an overlapping process performed on the plurality of nerve fibers extracted from the first tracking images, and the nerve fibers more similar to the structure of the nerve fasciculus skeleton are selected to obtain a specific fasciculus of the subject. Thus, the technical solution of the present disclosure can be used to improve the sensitivity of fiber tracking and be useful for improvement of preoperative assessment and surgical navigation.

Abstract: A technology for calibrating device-end operational information of a data storage system is shown. A controller operates a non-volatile memory with reference to operational information. A second type of logical address requested by the host that is different from the first type of logical address used in operating a file system of a host is introduced. As indicated by the second type of logical address, the controller receives calibration information from the host and calibrates the operational information based on the calibration information.

Abstract: The present disclosure illustrates a method and an apparatus of fiber tracking, and non-transitory computer-readable medium thereof. In an embodiment, a fiber tracking process is performed on a diffusion magnetic resonance image of a subject's brain based on validated and better tracking parameters, so as to obtain first tracking images, nerve fibers between two first regions of interest in each of the first tracking images are extracted, a nerve fasciculus skeleton is established based on an overlapping process performed on the plurality of nerve fibers extracted from the first tracking images, and the nerve fibers more similar to the structure of the nerve fasciculus skeleton are selected to obtain a specific fasciculus of the subject. Thus, the technical solution of the present disclosure can be used to improve the sensitivity of fiber tracking and be useful for improvement of preoperative assessment and surgical navigation.

Abstract: A detection method applied to a storage device including transmitting a Devslp command to a signal pin of the storage device; pulling high the voltage level at a control pin of the storage device when a first response corresponding to the Devslp command is received to enable the storage device to enter a sleep mode; pulling low the voltage level at the control pin when a first predetermined period has elapsed; transmitting a Comwake signal to the signal pin; and determining that the sleep mode of the device under test meets a specification when the storage device receives a second response corresponding to the Comwake signal in a second predetermined period.

Abstract: A method is presented for responding to user input by displaying when a circuit has a property expressed by an assertion based on data indicating values of signals of the circuit at a succession of times. The assertion expresses the property as a first sequence of expressions, and separately defines for each expression a corresponding evaluation time relative to the succession of times at which the expression is to be evaluated. The circuit has the property only if every expression of the first sequence evaluates true at its corresponding evaluation time. The method includes displaying a representation of each expression of the first sequence and identifying each variable that caused that expression to evaluate false and distinctively marking that variable's symbol relative to other variable symbols within the display for each expression of the first sequence that evaluates false at its corresponding evaluation time.

Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.

Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.

Abstract: A firmware update method applied to a host device and a peripheral device, wherein the peripheral device includes a memory device and a controller. The firmware update method includes: transmitting a first firmware data sector to a peripheral device from the host device, wherein the first firmware data sector has a first mode parameter; and retransmitting the first firmware data sector having a second mode parameter to the peripheral device from the host device after an interruption event has occurred on the memory device during the transmission.

Abstract: A firmware update method applied to a host device and a peripheral device, wherein the peripheral device includes a memory device and a controller. The firmware update method includes: transmitting a first firmware data sector to a peripheral device from the host device, wherein the first firmware data sector has a first mode parameter; and retransmitting the first firmware data sector having a second mode parameter to the peripheral device from the host device after an interruption event has occurred on the memory device during the transmission.

Abstract: A firmware update method applied to a host device and a peripheral device, wherein the peripheral device includes a memory device and a controller. The firmware update method includes: transmitting a first firmware data sector to a peripheral device from the host device, wherein the first firmware data sector has a first mode parameter; and retransmitting the first firmware data sector having a second mode parameter to the peripheral device from the host device after an interruption event has occurred on the memory device during the transmission.

Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.

Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.

Abstract: A firmware update method applied to a host device and a peripheral device, wherein the peripheral device includes a memory device and a controller. The firmware update method includes: transmitting a first firmware data sector to a peripheral device from the host device, wherein the first firmware data sector has a first mode parameter; and retransmitting the first firmware data sector having a second mode parameter to the peripheral device from the host device after an interruption event has occurred on the memory device during the transmission.

Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.

Abstract: A detection method applied to a storage device including transmitting a Devslp command to a signal pin of the storage device; pulling high the voltage level at a control pin of the storage device when a first response corresponding to the Devslp command is received to enable the storage device to enter a sleep mode; pulling low the voltage level at the control pin when a first predetermined period has elapsed; transmitting a Comwake signal to the signal pin; and determining that the sleep mode of the device under test meets a specification when the storage device receives a second response corresponding to the Comwake signal in a second predetermined period.

Abstract: The invention provides a flash memory controller. In one embodiment, the flash memory controller is coupled to a plurality of flash memories, and comprises a driving current generator and a processor. The driving current generator generates a driving current to drive the flash memories. The processor calculates the total number of flash memories, determines a driving current value according to the total number of flash memories, and directs the driving current generator to generate the driving current with a level greater than or equal to the driving current value. The driving current value is determined by the processor to be increased with an increase of the total number of flash memories.